diff --git a/src/main/scala/millfork/compiler/z80/Z80BulkMemoryOperations.scala b/src/main/scala/millfork/compiler/z80/Z80BulkMemoryOperations.scala
index 56c3e103..b55bf040 100644
--- a/src/main/scala/millfork/compiler/z80/Z80BulkMemoryOperations.scala
+++ b/src/main/scala/millfork/compiler/z80/Z80BulkMemoryOperations.scala
@@ -223,8 +223,8 @@ object Z80BulkMemoryOperations {
         case "|=" => (ZOpcode.OR, false, None)
         case "&=" => (ZOpcode.AND, false, None)
         case "^=" => (ZOpcode.XOR, false, None)
-        case "<<=" => (ZOpcode.SLA, false, Some(RLC, 0xfe))
-        case ">>=" => (ZOpcode.SRL, false, Some(RRC, 0x7f))
+        case "<<=" => (ZOpcode.SLA, false, Some(RL, 0xfe))
+        case ">>=" => (ZOpcode.SRL, false, Some(RR, 0x7f))
         case _ => return None
       }
       shift match {
diff --git a/src/main/scala/millfork/compiler/z80/Z80Shifting.scala b/src/main/scala/millfork/compiler/z80/Z80Shifting.scala
index 8fa6029e..9aa4cb1f 100644
--- a/src/main/scala/millfork/compiler/z80/Z80Shifting.scala
+++ b/src/main/scala/millfork/compiler/z80/Z80Shifting.scala
@@ -29,7 +29,7 @@ object Z80Shifting {
       if (extendedOps) {
         if (left) ZOpcode.SLA else ZOpcode.SRL
       } else {
-        if (left) ZOpcode.RLC else ZOpcode.RRC
+        if (left) ZOpcode.RL else ZOpcode.RR
       }
     val l = Z80ExpressionCompiler.compileToA(ctx, lhs)
     env.eval(rhs) match {
@@ -57,7 +57,7 @@ object Z80Shifting {
       if (extendedOps) {
         if (left) ZOpcode.SLA else ZOpcode.SRL
       } else {
-        if (left) ZOpcode.RLC else ZOpcode.RRC
+        if (left) ZOpcode.RL else ZOpcode.RR
       }
     env.eval(rhs) match {
       case Some(NumericConstant(i, _)) =>
@@ -123,23 +123,23 @@ object Z80Shifting {
             if (extendedOps) {
               l ++ (0L until i).flatMap(_ => List(
                 ZLine.register(ZOpcode.SRL, ZRegister.H),
-                ZLine.register(ZOpcode.RRC, ZRegister.L)
+                ZLine.register(ZOpcode.RR, ZRegister.L)
               ))
             } else {
               l ++ (1L until i).flatMap(_ => List(
                 ZLine.ld8(ZRegister.A, ZRegister.H),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 ZLine.ld8(ZRegister.H, ZRegister.A),
                 ZLine.ld8(ZRegister.A, ZRegister.L),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 ZLine.ld8(ZRegister.L, ZRegister.A)
               )) ++ List(
                 ZLine.ld8(ZRegister.A, ZRegister.H),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 ZLine.imm8(ZOpcode.AND, (0xff >> i) & 0xff),
                 ZLine.ld8(ZRegister.H, ZRegister.A),
                 ZLine.ld8(ZRegister.A, ZRegister.L),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 //                ZLine.imm8(ZOpcode.AND, (0xff << (i - 8)) & 0xff), // TODO: properly mask the low byte!!!
                 ZLine.ld8(ZRegister.L, ZRegister.A)
               )
@@ -153,30 +153,30 @@ object Z80Shifting {
             if (left) {
               List(
                 ZLine.register(ZOpcode.SLA, ZRegister.L),
-                ZLine.register(ZOpcode.RLC, ZRegister.H))
+                ZLine.register(ZOpcode.RL, ZRegister.H))
             } else {
               List(
                 ZLine.register(ZOpcode.SRL, ZRegister.H),
-                ZLine.register(ZOpcode.RRC, ZRegister.L))
+                ZLine.register(ZOpcode.RR, ZRegister.L))
             }
           } else {
             if (left) {
               List(
                 ZLine.ld8(ZRegister.A, ZRegister.L),
-                ZLine.register(ZOpcode.RLC, ZRegister.A),
+                ZLine.register(ZOpcode.RL, ZRegister.A),
                 ZLine.imm8(ZOpcode.AND, 0xfe),
                 ZLine.ld8(ZRegister.L, ZRegister.A),
                 ZLine.ld8(ZRegister.A, ZRegister.H),
-                ZLine.register(ZOpcode.RLC, ZRegister.A),
+                ZLine.register(ZOpcode.RL, ZRegister.A),
                 ZLine.ld8(ZRegister.H, ZRegister.A))
             } else {
               List(
                 ZLine.ld8(ZRegister.A, ZRegister.H),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 ZLine.imm8(ZOpcode.AND, 0x7f),
                 ZLine.ld8(ZRegister.H, ZRegister.A),
                 ZLine.ld8(ZRegister.A, ZRegister.L),
-                ZLine.register(ZOpcode.RRC, ZRegister.A),
+                ZLine.register(ZOpcode.RR, ZRegister.A),
                 ZLine.ld8(ZRegister.L, ZRegister.A))
             }
           }
diff --git a/src/main/scala/millfork/output/Z80Assembler.scala b/src/main/scala/millfork/output/Z80Assembler.scala
index dea2f3ec..09ea0537 100644
--- a/src/main/scala/millfork/output/Z80Assembler.scala
+++ b/src/main/scala/millfork/output/Z80Assembler.scala
@@ -73,6 +73,10 @@ class Z80Assembler(program: Program,
       case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) =>
         writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
         index + 1
+      case ZLine(SBC_16, TwoRegisters(ZRegister.HL, reg), _, _) =>
+        writeByte(bank, index, 0xed)
+        writeByte(bank, index + 1, 0x42 + 0x10 * internalRegisterIndex(reg))
+        index + 2
       case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) =>
         writeByte(bank, index, 1 + 16 * internalRegisterIndex(target))
         writeWord(bank, index + 1, param)
@@ -390,10 +394,10 @@ object Z80Assembler {
     oneRegister(POP) = One(0xc1, 0x10)
     oneRegister(PUSH) = One(0xc5, 0x10)
 
-    cbOneRegister(RL) = One(0x10, 1)
     cbOneRegister(RLC) = One(0, 1)
-    cbOneRegister(RR) = One(8, 1)
-    cbOneRegister(RRC) = One(0x18, 1)
+    cbOneRegister(RRC) = One(8, 1)
+    cbOneRegister(RL) = One(0x10, 1)
+    cbOneRegister(RR) = One(0x18, 1)
     cbOneRegister(SLA) = One(0x20, 1)
     cbOneRegister(SRA) = One(0x28, 1)
     cbOneRegister(SLL) = One(0x30, 1)