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Fix Z80 shifting
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parent
e5ee32f7d6
commit
57bde60ced
@ -223,8 +223,8 @@ object Z80BulkMemoryOperations {
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case "|=" => (ZOpcode.OR, false, None)
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case "|=" => (ZOpcode.OR, false, None)
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case "&=" => (ZOpcode.AND, false, None)
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case "&=" => (ZOpcode.AND, false, None)
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case "^=" => (ZOpcode.XOR, false, None)
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case "^=" => (ZOpcode.XOR, false, None)
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case "<<=" => (ZOpcode.SLA, false, Some(RLC, 0xfe))
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case "<<=" => (ZOpcode.SLA, false, Some(RL, 0xfe))
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case ">>=" => (ZOpcode.SRL, false, Some(RRC, 0x7f))
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case ">>=" => (ZOpcode.SRL, false, Some(RR, 0x7f))
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case _ => return None
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case _ => return None
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}
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}
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shift match {
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shift match {
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@ -29,7 +29,7 @@ object Z80Shifting {
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if (extendedOps) {
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if (extendedOps) {
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if (left) ZOpcode.SLA else ZOpcode.SRL
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if (left) ZOpcode.SLA else ZOpcode.SRL
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} else {
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} else {
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if (left) ZOpcode.RLC else ZOpcode.RRC
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if (left) ZOpcode.RL else ZOpcode.RR
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}
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}
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val l = Z80ExpressionCompiler.compileToA(ctx, lhs)
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val l = Z80ExpressionCompiler.compileToA(ctx, lhs)
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env.eval(rhs) match {
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env.eval(rhs) match {
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@ -57,7 +57,7 @@ object Z80Shifting {
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if (extendedOps) {
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if (extendedOps) {
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if (left) ZOpcode.SLA else ZOpcode.SRL
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if (left) ZOpcode.SLA else ZOpcode.SRL
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} else {
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} else {
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if (left) ZOpcode.RLC else ZOpcode.RRC
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if (left) ZOpcode.RL else ZOpcode.RR
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}
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}
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env.eval(rhs) match {
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env.eval(rhs) match {
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case Some(NumericConstant(i, _)) =>
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case Some(NumericConstant(i, _)) =>
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@ -123,23 +123,23 @@ object Z80Shifting {
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if (extendedOps) {
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if (extendedOps) {
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l ++ (0L until i).flatMap(_ => List(
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l ++ (0L until i).flatMap(_ => List(
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ZLine.register(ZOpcode.SRL, ZRegister.H),
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ZLine.register(ZOpcode.SRL, ZRegister.H),
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ZLine.register(ZOpcode.RRC, ZRegister.L)
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ZLine.register(ZOpcode.RR, ZRegister.L)
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))
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))
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} else {
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} else {
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l ++ (1L until i).flatMap(_ => List(
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l ++ (1L until i).flatMap(_ => List(
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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ZLine.ld8(ZRegister.L, ZRegister.A)
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ZLine.ld8(ZRegister.L, ZRegister.A)
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)) ++ List(
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)) ++ List(
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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ZLine.imm8(ZOpcode.AND, (0xff >> i) & 0xff),
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ZLine.imm8(ZOpcode.AND, (0xff >> i) & 0xff),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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// ZLine.imm8(ZOpcode.AND, (0xff << (i - 8)) & 0xff), // TODO: properly mask the low byte!!!
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// ZLine.imm8(ZOpcode.AND, (0xff << (i - 8)) & 0xff), // TODO: properly mask the low byte!!!
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ZLine.ld8(ZRegister.L, ZRegister.A)
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ZLine.ld8(ZRegister.L, ZRegister.A)
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)
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)
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@ -153,30 +153,30 @@ object Z80Shifting {
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if (left) {
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if (left) {
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List(
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List(
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ZLine.register(ZOpcode.SLA, ZRegister.L),
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ZLine.register(ZOpcode.SLA, ZRegister.L),
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ZLine.register(ZOpcode.RLC, ZRegister.H))
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ZLine.register(ZOpcode.RL, ZRegister.H))
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} else {
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} else {
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List(
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List(
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ZLine.register(ZOpcode.SRL, ZRegister.H),
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ZLine.register(ZOpcode.SRL, ZRegister.H),
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ZLine.register(ZOpcode.RRC, ZRegister.L))
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ZLine.register(ZOpcode.RR, ZRegister.L))
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}
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}
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} else {
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} else {
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if (left) {
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if (left) {
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List(
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List(
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.register(ZOpcode.RLC, ZRegister.A),
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ZLine.register(ZOpcode.RL, ZRegister.A),
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ZLine.imm8(ZOpcode.AND, 0xfe),
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ZLine.imm8(ZOpcode.AND, 0xfe),
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ZLine.ld8(ZRegister.L, ZRegister.A),
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ZLine.ld8(ZRegister.L, ZRegister.A),
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.register(ZOpcode.RLC, ZRegister.A),
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ZLine.register(ZOpcode.RL, ZRegister.A),
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ZLine.ld8(ZRegister.H, ZRegister.A))
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ZLine.ld8(ZRegister.H, ZRegister.A))
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} else {
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} else {
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List(
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List(
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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ZLine.imm8(ZOpcode.AND, 0x7f),
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ZLine.imm8(ZOpcode.AND, 0x7f),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.register(ZOpcode.RRC, ZRegister.A),
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ZLine.register(ZOpcode.RR, ZRegister.A),
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ZLine.ld8(ZRegister.L, ZRegister.A))
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ZLine.ld8(ZRegister.L, ZRegister.A))
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}
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}
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}
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}
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@ -73,6 +73,10 @@ class Z80Assembler(program: Program,
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case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) =>
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case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) =>
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writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
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writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
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index + 1
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index + 1
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case ZLine(SBC_16, TwoRegisters(ZRegister.HL, reg), _, _) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x42 + 0x10 * internalRegisterIndex(reg))
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index + 2
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case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) =>
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case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) =>
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writeByte(bank, index, 1 + 16 * internalRegisterIndex(target))
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writeByte(bank, index, 1 + 16 * internalRegisterIndex(target))
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writeWord(bank, index + 1, param)
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writeWord(bank, index + 1, param)
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@ -390,10 +394,10 @@ object Z80Assembler {
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oneRegister(POP) = One(0xc1, 0x10)
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oneRegister(POP) = One(0xc1, 0x10)
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oneRegister(PUSH) = One(0xc5, 0x10)
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oneRegister(PUSH) = One(0xc5, 0x10)
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cbOneRegister(RL) = One(0x10, 1)
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cbOneRegister(RLC) = One(0, 1)
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cbOneRegister(RLC) = One(0, 1)
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cbOneRegister(RR) = One(8, 1)
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cbOneRegister(RRC) = One(8, 1)
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cbOneRegister(RRC) = One(0x18, 1)
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cbOneRegister(RL) = One(0x10, 1)
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cbOneRegister(RR) = One(0x18, 1)
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cbOneRegister(SLA) = One(0x20, 1)
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cbOneRegister(SLA) = One(0x20, 1)
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cbOneRegister(SRA) = One(0x28, 1)
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cbOneRegister(SRA) = One(0x28, 1)
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cbOneRegister(SLL) = One(0x30, 1)
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cbOneRegister(SLL) = One(0x30, 1)
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