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Make some tests work on LR35902

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This commit is contained in:
Karol Stasiak 2018-07-27 19:10:15 +02:00
parent 1948c38e04
commit 600e49cf49
2 changed files with 15 additions and 4 deletions
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18
src/test/scala/millfork/test/emu/EmuZ80Run.scala
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@ -24,7 +24,7 @@ import org.scalatest.Matchers
class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimization], assemblyOptimizations: List[AssemblyOptimization[ZLine]]) extends Matchers { class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimization], assemblyOptimizations: List[AssemblyOptimization[ZLine]]) extends Matchers {
def inline: Boolean = false def inline: Boolean = false
private val TooManyCycles: Long = 1000000 private val TooManyCycles: Long = 1500000
def apply(source: String): MemoryBank = { def apply(source: String): MemoryBank = {
apply2(source)._2 apply2(source)._2
@ -132,6 +132,7 @@ class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimizatio
cpu.getRegisters.setPC(0x1f0) cpu.getRegisters.setPC(0x1f0)
while (cpu.getState != Cpu.State.HALTED) { while (cpu.getState != Cpu.State.HALTED) {
cpu.tick() cpu.tick()
// dump(cpu)
ticks += 4 ticks += 4
ticks should be < TooManyCycles ticks should be < TooManyCycles
} }
@ -152,9 +153,18 @@ class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimizatio
def dump(cpu: Z80Core): Unit = { def dump(cpu: Z80Core): Unit = {
val a = cpu.getRegisterValue(CPUConstants.RegisterNames.A) val a = cpu.getRegisterValue(CPUConstants.RegisterNames.A)
val bc = cpu.getRegisterValue(CPUConstants.RegisterNames.A) val bc = cpu.getRegisterValue(CPUConstants.RegisterNames.BC)
val de = cpu.getRegisterValue(CPUConstants.RegisterNames.A) val de = cpu.getRegisterValue(CPUConstants.RegisterNames.DE)
val hl = cpu.getRegisterValue(CPUConstants.RegisterNames.A) val hl = cpu.getRegisterValue(CPUConstants.RegisterNames.HL)
println(f"A=$a%02x,BC=$bc%04x,DE=$de%04x,HL=$hl%04x")
}
def dump(cpu: Cpu): Unit = {
val regs = cpu.getRegisters
val a = regs.getA
val bc = regs.getBC
val de = regs.getDE
val hl = regs.getHL
println(f"A=$a%02x,BC=$bc%04x,DE=$de%04x,HL=$hl%04x") println(f"A=$a%02x,BC=$bc%04x,DE=$de%04x,HL=$hl%04x")
} }

1
src/test/scala/millfork/test/emu/GameboyMemory.scala
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@ -11,6 +11,7 @@ case class GameboyMemory(memoryBank: MemoryBank) extends AddressSpace {
override def setByte(address: Int, data: Int): Unit = { override def setByte(address: Int, data: Int): Unit = {
// if (!memoryBank.writeable(address)) throw new RuntimeException("Can't write to $" + address.toHexString) // if (!memoryBank.writeable(address)) throw new RuntimeException("Can't write to $" + address.toHexString)
// println(s"Written: ${data.toHexString} to ${address.toHexString}")
memoryBank.output(address) = data.toByte memoryBank.output(address) = data.toByte
} }