From 6774c283ae31edc955c03d1eacfee84fade652ec Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Sat, 18 Jan 2020 00:09:06 +0100 Subject: [PATCH] 6502: Add KIL instruction (fixes #37) --- docs/abi/undocumented.md | 2 + .../millfork/assembly/mos/AssemblyLine.scala | 2 +- .../scala/millfork/assembly/mos/Opcode.scala | 3 +- .../mos/opt/FlowAnalyzerForImplied.scala | 1 + .../ReverseFlowAnalyzerPerImpliedOpcode.scala | 6 ++ .../scala/millfork/output/MosAssembler.scala | 2 + .../scala/millfork/test/AssemblySuite.scala | 82 ++++++++++++++++++- 7 files changed, 95 insertions(+), 3 deletions(-) diff --git a/docs/abi/undocumented.md b/docs/abi/undocumented.md index 9c71ac01..cd9515a1 100644 --- a/docs/abi/undocumented.md +++ b/docs/abi/undocumented.md @@ -24,6 +24,8 @@ Millfork supports multiple mnemonics per opcode. The default one is given first: * **ISC**, INS +* **KIL** + * **LAS** * **LAX** diff --git a/src/main/scala/millfork/assembly/mos/AssemblyLine.scala b/src/main/scala/millfork/assembly/mos/AssemblyLine.scala index 8a788b1c..b9dadaa7 100644 --- a/src/main/scala/millfork/assembly/mos/AssemblyLine.scala +++ b/src/main/scala/millfork/assembly/mos/AssemblyLine.scala @@ -358,7 +358,7 @@ object OpcodeClasses { STZ, PHX, PHY, PLX, PLY, TSB, TRB, STZ_W, PHX_W, PHY_W, PLX_W, PLY_W, TSB_W, TRB_W, SLO, RLA, SRE, RRA, SAX, LAX, DCP, ISC, - ANC, ALR, ARR, XAA, LXA, SBX, + ANC, ALR, ARR, XAA, LXA, SBX, KIL, CPZ, LDZ, INZ, DEZ, TAZ, TZA, TYS, TSY, TBA, diff --git a/src/main/scala/millfork/assembly/mos/Opcode.scala b/src/main/scala/millfork/assembly/mos/Opcode.scala index 3f6c2fec..f438c8c0 100644 --- a/src/main/scala/millfork/assembly/mos/Opcode.scala +++ b/src/main/scala/millfork/assembly/mos/Opcode.scala @@ -72,7 +72,7 @@ object Opcode extends Enumeration { // illegals: LXA, XAA, ANC, ARR, ALR, SBX, LAX, SAX, RLA, RRA, SLO, SRE, DCP, ISC, - TAS, LAS, SHX, SHY, AHX, + TAS, LAS, SHX, SHY, AHX, KIL, // 65C02: STZ, PHX, PHY, PLX, PLY, @@ -222,6 +222,7 @@ object Opcode extends Enumeration { case "ISC" => ISC case "JMP" => JMP case "JSR" => JSR + case "KIL" => KIL case "LAS" => LAS case "LAX" => LAX case "LDA" => LDA diff --git a/src/main/scala/millfork/assembly/mos/opt/FlowAnalyzerForImplied.scala b/src/main/scala/millfork/assembly/mos/opt/FlowAnalyzerForImplied.scala index fbda7956..18ae6bce 100644 --- a/src/main/scala/millfork/assembly/mos/opt/FlowAnalyzerForImplied.scala +++ b/src/main/scala/millfork/assembly/mos/opt/FlowAnalyzerForImplied.scala @@ -15,6 +15,7 @@ object FlowAnalyzerForImplied { RTI -> identity, SEI -> identity, CLI -> identity, + KIL -> identity, TXS -> (_.copy(eqSX = true, eqSpX = false)), PHP -> (_.copy(eqSX = false)), PHA -> (_.copy(eqSX = false)), diff --git a/src/main/scala/millfork/assembly/mos/opt/ReverseFlowAnalyzerPerImpliedOpcode.scala b/src/main/scala/millfork/assembly/mos/opt/ReverseFlowAnalyzerPerImpliedOpcode.scala index e481ec51..20de9e4e 100644 --- a/src/main/scala/millfork/assembly/mos/opt/ReverseFlowAnalyzerPerImpliedOpcode.scala +++ b/src/main/scala/millfork/assembly/mos/opt/ReverseFlowAnalyzerPerImpliedOpcode.scala @@ -38,6 +38,12 @@ object ReverseFlowAnalyzerPerImpiedOpcode { CLI -> identity, WAI -> identity, STP -> identity, + KIL -> (_ => CpuImportance( + a = Unimportant, ah = Unimportant, + x = Unimportant, y = Unimportant, iz = Unimportant, + r0 = Unimportant, r1 = Unimportant, r2 = Unimportant, r3 = Unimportant, + z = Unimportant, n = Unimportant, c = Unimportant, v = Unimportant, d = Unimportant, + m = Unimportant, w = Unimportant)), BRK -> (_ => finalImportance), COP -> (_ => finalImportance), RTS -> (_ => finalImportance), diff --git a/src/main/scala/millfork/output/MosAssembler.scala b/src/main/scala/millfork/output/MosAssembler.scala index e89a22ae..16b6f000 100644 --- a/src/main/scala/millfork/output/MosAssembler.scala +++ b/src/main/scala/millfork/output/MosAssembler.scala @@ -542,6 +542,8 @@ object MosAssembler { op(STY, ZeroPageX, 0x94) op(STY, Absolute, 0x8C) + il(KIL, Implied, 0x02) // there are multiple candidates and some others could be a better choice, but whatever, 02 is fine + il(LAX, ZeroPage, 0xA7) il(LAX, ZeroPageY, 0xB7) il(LAX, Absolute, 0xAF) diff --git a/src/test/scala/millfork/test/AssemblySuite.scala b/src/test/scala/millfork/test/AssemblySuite.scala index 81822745..426059d7 100644 --- a/src/test/scala/millfork/test/AssemblySuite.scala +++ b/src/test/scala/millfork/test/AssemblySuite.scala @@ -1,6 +1,6 @@ package millfork.test import millfork.Cpu -import millfork.test.emu.{EmuBenchmarkRun, EmuCrossPlatformBenchmarkRun, EmuOptimizedCmosRun, EmuOptimizedHudsonRun, EmuOptimizedRun, EmuUnoptimizedHudsonRun} +import millfork.test.emu.{EmuBenchmarkRun, EmuCrossPlatformBenchmarkRun, EmuOptimizedCmosRun, EmuOptimizedHudsonRun, EmuOptimizedRun, EmuUndocumentedRun, EmuUnoptimizedCrossPlatformRun, EmuUnoptimizedHudsonRun} import org.scalatest.{AppendedClues, FunSuite, Matchers} /** @@ -226,6 +226,86 @@ class AssemblySuite extends FunSuite with Matchers with AppendedClues { } } + test("Undocumented opcodes") { + EmuUndocumentedRun( + """ + | asm void main() { + | rts + | kil + | slo $4 + | slo $400 + | slo $4,x + | slo $400,x + | slo $400,y + | slo ($4,x) + | slo ($4),y + | rla $4 + | rla $400 + | rla $4,x + | rla $400,x + | rla $400,y + | rla ($4,x) + | rla ($4),y + | rra $4 + | rra $400 + | rra $4,x + | rra $400,x + | rra $400,y + | rra ($4,x) + | rra ($4),y + | sre $4 + | sre $400 + | sre $4,x + | sre $400,x + | sre $400,y + | sre ($4,x) + | sre ($4),y + | dcp $4 + | dcp $400 + | dcp $4,x + | dcp $400,x + | dcp $400,y + | dcp ($4,x) + | dcp ($4),y + | isc $4 + | isc $400 + | isc $4,x + | isc $400,x + | isc $400,y + | isc ($4,x) + | isc ($4),y + | lax $4 + | lax $4,y + | lax $400 + | lax $400,y + | lax ($4,x) + | lax ($4),y + | sax $4 + | sax $4,y + | sax $400 + | sax ($4,x) + | anc #$4 + | alr #$4 + | arr #$4 + | xaa #$4 + | lxa #$4 + | sbx #$4 + | ahx ($4),y + | ahx $400,y + | shy $400,x + | shx $400,y + | tas $400,y + | las $400,y + | bne $300 + | brk #4 + | bne #4 + | rts + | } + | + |""".stripMargin + ) + } + test("HuC6280 opcodes") { EmuOptimizedHudsonRun( """