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Z80: More arithmetic optimizations

This commit is contained in:
Karol Stasiak 2018-08-01 15:32:11 +02:00
parent 0326c7a73b
commit 6b02c5178a
3 changed files with 34 additions and 3 deletions

@ -377,7 +377,7 @@ object AlwaysGoodI80Optimizations {
(Elidable & HasOpcodeIn(Set(ADD, OR, XOR, SUB)) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => Nil),
(Elidable & HasOpcode(AND) & Has8BitImmediate(0xff) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => Nil),
(Elidable & HasOpcode(AND) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => List(ZLine.ldImm8(ZRegister.A, 0))),
(Elidable & HasOpcode(AND) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => List(ZLine.ldImm8(ZRegister.A, 0))),
(Elidable & HasOpcode(XOR) & Has8BitImmediate(0xff) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => List(ZLine.implied(CPL))),
(Elidable & HasOpcode(OR) & Match8BitImmediate(1) & MatchRegister(ZRegister.A, 0)) ~
@ -467,7 +467,31 @@ object AlwaysGoodI80Optimizations {
(Elidable & Is8BitLoadTo(ZRegister.A)) ~
(Elidable & HasOpcode(SBC)) ~~> { code =>
List(code(1), code.last.copy(opcode = SUB))
}
},
(Elidable & HasOpcode(ADD) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { _ =>
List(ZLine.register(OR, A))
},
(Elidable & HasOpcode(SUB) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { _ =>
List(ZLine.register(OR, A))
},
(Elidable & HasOpcode(ADC) & Has8BitImmediate(0) & HasClear(ZFlag.C) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { _ =>
List(ZLine.register(OR, A))
},
(Elidable & HasOpcode(ADC) & HasClear(ZFlag.C)) ~~> { code =>
code.map(_.copy(opcode = ADD))
},
(Elidable & HasOpcode(SBC) & HasClear(ZFlag.C)) ~~> { code =>
code.map(_.copy(opcode = SUB))
},
(Elidable & HasOpcodeIn(Set(OR, XOR)) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlags) ~~> ( _ => Nil),
(Elidable & HasOpcode(OR) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => Nil),
)

@ -51,6 +51,10 @@ object CoarseFlowAnalyzer {
case ZLine(AND, OneRegister(s), _, _) =>
currentStatus = currentStatus.copy(a = (currentStatus.a <*> currentStatus.getRegister(s)) ((m, n) => (m & n) & 0xff),
cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
case ZLine(OR, OneRegister(ZRegister.A), _, _) =>
currentStatus = currentStatus.copy(cf = Status.SingleFalse, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
case ZLine(XOR, OneRegister(ZRegister.A), _, _) =>
currentStatus = currentStatus.copy(a = Status.SingleZero, cf = Status.SingleFalse, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
case ZLine(OR, OneRegister(s), _, _) =>
currentStatus = currentStatus.copy(a = (currentStatus.a <*> currentStatus.getRegister(s)) ((m, n) => (m | n) & 0xff),
cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
@ -122,6 +126,9 @@ object CoarseFlowAnalyzer {
zf = AnyStatus,
pf = AnyStatus, hf = Status.SingleFalse)
case ZLine(SCF, _, _, _) => currentStatus.copy(cf = Status.SingleTrue)
case ZLine(CCF, _, _, _) => currentStatus.copy(cf = currentStatus.cf.negate)
case ZLine(opcode, registers, _, _) =>
currentStatus = currentStatus.copy(cf = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus)
if (ZOpcodeClasses.ChangesAAlways(opcode)) currentStatus = currentStatus.copy(a = AnyStatus)

@ -655,7 +655,7 @@ case class HasClear(flag: ZFlag.Value) extends AssemblyLinePattern {
FlowInfoRequirement.assertForward(needsFlowInfo)
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean =
flowInfo.statusBefore.getFlag(flag).exists(_ == true)
flowInfo.statusBefore.getFlag(flag).exists(_ == false)
}
case object Anything extends TrivialAssemblyLinePattern {