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Code Issues Projects Releases Wiki Activity

Don't deduplicate non-elidable code

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This commit is contained in:
Karol Stasiak 2018-10-04 23:23:04 +02:00
parent ed38b00031
commit 6b43f73f57
3 changed files with 9 additions and 9 deletions
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2
src/main/scala/millfork/output/MosDeduplicate.scala
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@ -51,7 +51,7 @@ class MosDeduplicate(env: Environment, options: CompilationOptions) extends Dedu
private val badAddressingModes = Set(Stack, IndexedSY, AbsoluteIndexedX, Indirect, LongIndirect) private val badAddressingModes = Set(Stack, IndexedSY, AbsoluteIndexedX, Indirect, LongIndirect)
override def isExtractable(line: AssemblyLine): Boolean = override def isExtractable(line: AssemblyLine): Boolean =
goodOpcodes(line.opcode) && !badAddressingModes(line.addrMode) line.elidable && goodOpcodes(line.opcode) && !badAddressingModes(line.addrMode)
override def isBadExtractedCodeHead(head: AssemblyLine): Boolean = false override def isBadExtractedCodeHead(head: AssemblyLine): Boolean = false

4
src/main/scala/millfork/output/Z80Deduplicate.scala
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@ -49,13 +49,13 @@ class Z80Deduplicate(env: Environment, options: CompilationOptions) extends Dedu
) )
override def isExtractable(line: ZLine): Boolean = { override def isExtractable(line: ZLine): Boolean = {
alwaysGoodOpcodes(line.opcode) || line.elidable && (alwaysGoodOpcodes(line.opcode) ||
conditionallyGoodOpcodes(line.opcode) && (line.registers match { conditionallyGoodOpcodes(line.opcode) && (line.registers match {
case OneRegister(SP) => false case OneRegister(SP) => false
case TwoRegisters(_, SP) => false case TwoRegisters(_, SP) => false
case TwoRegisters(SP, _) => false case TwoRegisters(SP, _) => false
case _ => true case _ => true
}) }))
} }
override def isBadExtractedCodeHead(head: ZLine): Boolean = false override def isBadExtractedCodeHead(head: ZLine): Boolean = false

12
src/test/scala/millfork/test/AssemblySuite.scala
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@ -178,28 +178,28 @@ class AssemblySuite extends FunSuite with Matchers with AppendedClues {
| e() | e()
| f() | f()
| } | }
| noinline void a() { | void a() {
| port = 1 | port = 1
| } | }
| noinline void b() { | void b() {
| port_alt = 2 | port_alt = 2
| } | }
| noinline asm void c() { | asm void c() {
| lda #3 | lda #3
| sta 1 | sta 1
| rts | rts
| } | }
| noinline asm void d() { | asm void d() {
| lda #4 | lda #4
| sta port | sta port
| rts | rts
| } | }
| noinline asm void e() { | asm void e() {
| lda #5 | lda #5
| sta port_addr | sta port_addr
| rts | rts
| } | }
| noinline asm void f() { | asm void f() {
| lda #6 | lda #6
| sta port_alt | sta port_alt
| rts | rts