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Added ZeropagePseugoregister to default compilation flags
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@ -76,15 +76,27 @@ object Cpu extends Enumeration {
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import CompilationFlag._
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private val alwaysDefaultFlags = Set(
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VariableOverlap, CompactReturnDispatchParams, ZeropagePseudoregister
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)
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def defaultFlags(x: Cpu.Value): Set[CompilationFlag.Value] = x match {
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case StrictMos => Set(DecimalMode, PreventJmpIndirectBug, VariableOverlap, CompactReturnDispatchParams)
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case Mos => Set(DecimalMode, PreventJmpIndirectBug, VariableOverlap, CompactReturnDispatchParams)
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case Ricoh => Set(PreventJmpIndirectBug, VariableOverlap, CompactReturnDispatchParams)
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case StrictRicoh => Set(PreventJmpIndirectBug, VariableOverlap, CompactReturnDispatchParams)
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case Cmos => Set(DecimalMode, EmitCmosOpcodes, VariableOverlap, CompactReturnDispatchParams)
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case HuC6280 => Set(DecimalMode, EmitCmosOpcodes, EmitHudsonOpcodes, VariableOverlap, CompactReturnDispatchParams)
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case CE02 => Set(DecimalMode, EmitCmosOpcodes, Emit65CE02Opcodes, VariableOverlap, CompactReturnDispatchParams)
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case Sixteen => Set(DecimalMode, EmitCmosOpcodes, EmitEmulation65816Opcodes, EmitNative65816Opcodes, ReturnWordsViaAccumulator, VariableOverlap, CompactReturnDispatchParams)
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case StrictMos =>
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alwaysDefaultFlags ++ Set(DecimalMode, PreventJmpIndirectBug)
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case Mos =>
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alwaysDefaultFlags ++ Set(DecimalMode, PreventJmpIndirectBug)
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case Ricoh =>
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alwaysDefaultFlags ++ Set(PreventJmpIndirectBug)
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case StrictRicoh =>
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alwaysDefaultFlags ++ Set(PreventJmpIndirectBug)
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case Cmos =>
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alwaysDefaultFlags ++ Set(DecimalMode, EmitCmosOpcodes)
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case HuC6280 =>
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alwaysDefaultFlags ++ Set(DecimalMode, EmitCmosOpcodes, EmitHudsonOpcodes)
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case CE02 =>
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alwaysDefaultFlags ++ Set(DecimalMode, EmitCmosOpcodes, Emit65CE02Opcodes)
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case Sixteen =>
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alwaysDefaultFlags ++ Set(DecimalMode, EmitCmosOpcodes, EmitEmulation65816Opcodes, EmitNative65816Opcodes, ReturnWordsViaAccumulator)
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}
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def fromString(name: String): Cpu.Value = name match {
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