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6502: Word addition optimizations

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This commit is contained in:
Karol Stasiak 2019-10-23 12:56:48 +02:00
parent 010647682a
commit 72f8806c54
2 changed files with 30 additions and 4 deletions
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17
src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
View File

@ -2540,6 +2540,23 @@ object AlwaysGoodOptimizations {
code(8).copy(opcode = INC),
AssemblyLine.label(label))
},
(Elidable & HasOpcode(LDX) & HasImmediate(0) & HasClear(State.D)) ~
(Elidable & HasOpcode(BCC) & MatchParameter(14)) ~
(Elidable & HasOpcode(INX)) ~
(Elidable & HasOpcode(LABEL) & MatchParameter(14) & HasCallerCount(1)) ~
(Elidable & HasOpcode(STA) & Not(ConcernsX)) ~
(Elidable & HasOpcode(TXA)) ~
(Elidable & HasOpcode(CLC)) ~
(Elidable & HasOpcode(ADC)) ~
(Elidable & HasOpcode(STA) & DoesntMatterWhatItDoesWith(State.C, State.N, State.V, State.Z)) ~~> { (code, ctx) =>
val label = ctx.nextLabel("in")
List(
code(4), // STA
AssemblyLine.implied(TAX),
AssemblyLine.immediate(LDA, 0),
code(7), // ADC
code(8)) // STA
},
(Elidable & HasOpcode(LDX) & HasAddrMode(Immediate) & HasClear(State.D)) ~
(Elidable & HasOpcode(BCC) & MatchParameter(14)) ~
(Elidable & HasOpcode(INX)) ~

17
src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
View File

@ -65,11 +65,20 @@ object PseudoregisterBuiltIns {
case Some(ax) =>
niceReads.prepend(ax -> List(AssemblyLine.implied(TXA)))
if (!constant.isProvablyZero) {
if (constant.isQuiteNegative) {
niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
if (constant.loByte.quickSimplify.isProvablyZero) {
if (constant.isQuiteNegative) {
val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
niceReads += Nil -> List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.hiByte))
} else {
niceReads += Nil -> List(AssemblyLine.implied(CLC),AssemblyLine.immediate(ADC, constant.hiByte))
}
} else {
val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
if (constant.isQuiteNegative) {
val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
} else {
niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
}
}
}
case None =>