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(part 2) 6502: Do not optimize away register restoration in interrupt routines (fixes #19)

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Karol Stasiak
2019-11-13 19:08:50 +01:00
parent b10d8d7eeb
commit 7b040c280b
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala
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@@ -136,7 +136,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
val lastByte = if (zpRegisterSize % 2 != 0) { val lastByte = if (zpRegisterSize % 2 != 0) {
List( List(
AssemblyLine.implied(PLA), AssemblyLine.implied(PLA),
AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1), AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1).copy(elidability = Elidability.Volatile),
AssemblyLine.accu16) AssemblyLine.accu16)
} else { } else {
List(AssemblyLine.accu16) List(AssemblyLine.accu16)
@@ -144,7 +144,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
val remainingBytes = (zpRegisterSize.&(0xfe).-(2) to 0 by (-2)).flatMap { i => val remainingBytes = (zpRegisterSize.&(0xfe).-(2) to 0 by (-2)).flatMap { i =>
List( List(
AssemblyLine.implied(PLA_W), AssemblyLine.implied(PLA_W),
AssemblyLine.zeropage(STA_W, reg, i), AssemblyLine.zeropage(STA_W, reg, i).copy(elidability = Elidability.Volatile),
AssemblyLine.accu8) AssemblyLine.accu8)
} }
lastByte ++ remainingBytes lastByte ++ remainingBytes