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More optimizations
This commit is contained in:
Karol Stasiak
parent
91acbfae2f
commit
7e04312462
src
@ -53,6 +53,7 @@ object OptimizationPresets {
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LaterOptimizations.DoubleLoadToTheSameRegister,
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LaterOptimizations.DoubleLoadToDifferentRegisters,
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LaterOptimizations.DoubleLoadToTheSameRegister,
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LaterOptimizations.DoubleLoadToTwoRegistersWhenOneWillBeTrashed,
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EmptyMemoryStoreRemoval,
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AlwaysGoodOptimizations.PoinlessLoadBeforeAnotherLoad,
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AlwaysGoodOptimizations.IdempotentDuplicateRemoval,
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@ -63,6 +64,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.PointlessRegisterTransfersBeforeReturn,
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AlwaysGoodOptimizations.PointlessRegisterTransfersBeforeStore,
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AlwaysGoodOptimizations.PointlessStashingToIndexOverShortSafeBranch,
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AlwaysGoodOptimizations.PointlessStackStashing,
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AlwaysGoodOptimizations.RearrangeMath,
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EmptyMemoryStoreRemoval,
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AlwaysGoodOptimizations.PointlessLoadBeforeReturn,
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@ -101,6 +103,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.PointlessMathFromFlow,
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AlwaysGoodOptimizations.PointlessMathFromFlow,
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AlwaysGoodOptimizations.PointlessMathFromFlow,
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AlwaysGoodOptimizations.IncrementingIndexRegistersAfterTransfer,
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AlwaysGoodOptimizations.MathOperationOnTwoIdenticalMemoryOperands,
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LaterOptimizations.UseZeropageAddressingMode,
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@ -125,6 +128,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.FlagFlowAnalysis,
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AlwaysGoodOptimizations.IdempotentDuplicateRemoval,
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AlwaysGoodOptimizations.ImpossibleBranchRemoval,
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AlwaysGoodOptimizations.IncrementingIndexRegistersAfterTransfer,
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AlwaysGoodOptimizations.IndexSequenceOptimization,
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AlwaysGoodOptimizations.MathOperationOnTwoIdenticalMemoryOperands,
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AlwaysGoodOptimizations.ModificationOfJustWrittenValue,
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@ -141,6 +145,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.PointlessRegisterTransfers,
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AlwaysGoodOptimizations.PointlessRegisterTransfersBeforeCompare,
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AlwaysGoodOptimizations.PointlessRegisterTransfersBeforeReturn,
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AlwaysGoodOptimizations.PointlessStackStashing,
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AlwaysGoodOptimizations.PointlessStashingToIndexOverShortSafeBranch,
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AlwaysGoodOptimizations.PoinlessStoreBeforeStore,
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AlwaysGoodOptimizations.RearrangeMath,
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@ -192,6 +192,51 @@ object AlwaysGoodOptimizations {
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operationPairBuilder(DEY, INY, Not(ConcernsX) & Not(ReadsNOrZ)),
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)
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val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(PHA)) ~
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(Linear & Not(ConcernsStack) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(PLA)) ~~> { code =>
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code.head :: (code.drop(2).init :+ code.head)
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},
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(PHX)) ~
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(Linear & Not(ConcernsStack) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(PLX)) ~~> { code =>
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code.head :: (code.drop(2).init :+ code.head)
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},
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(PHY)) ~
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(Linear & Not(ConcernsStack) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(PLY)) ~~> { code =>
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code.head :: (code.drop(2).init :+ code.head)
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},
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)
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val IncrementingIndexRegistersAfterTransfer = new RuleBasedAssemblyOptimization("Incrementing index registers after transfer",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(CLC) & HasClear(State.D)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1)) ~
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(Elidable & HasOpcode(TAY) & DoesntMatterWhatItDoesWith(State.A, State.C)) ~~> { code =>
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List(AssemblyLine.implied(TAY), AssemblyLine.implied(INY))
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},
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(Elidable & HasOpcode(SEC) & HasClear(State.D)) ~
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(Elidable & HasOpcode(SBC) & HasImmediate(1)) ~
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(Elidable & HasOpcode(TAY) & DoesntMatterWhatItDoesWith(State.A, State.C)) ~~> { code =>
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List(AssemblyLine.implied(TAY), AssemblyLine.implied(DEY))
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},
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(Elidable & HasOpcode(CLC) & HasClear(State.D)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1)) ~
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(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.A, State.C)) ~~> { code =>
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List(AssemblyLine.implied(TAX), AssemblyLine.implied(INX))
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},
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(Elidable & HasOpcode(SEC) & HasClear(State.D)) ~
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(Elidable & HasOpcode(SBC) & HasImmediate(1)) ~
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(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.A, State.C)) ~~> { code =>
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List(AssemblyLine.implied(TAX), AssemblyLine.implied(DEX))
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},
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)
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val BranchInPlaceRemoval = new RuleBasedAssemblyOptimization("Branch in place",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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@ -253,7 +298,6 @@ object AlwaysGoodOptimizations {
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)
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// Optimizing Bxx to JMP is generally bad, but it may allow for better optimizations later
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// It's okay to undo it at a later stage, but it's not done yet
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val FlagFlowAnalysis = new RuleBasedAssemblyOptimization("Flag flow analysis",
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needsFlowInfo = FlowInfoRequirement.ForwardFlow,
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(HasSet(State.C) & HasOpcode(SEC) & Elidable) ~~> (_ => Nil),
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@ -14,6 +14,12 @@ import millfork.env.{Constant, NormalFunction, NumericConstant}
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//noinspection ZeroIndexToHead
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object LaterOptimizations {
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private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY)
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private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX)
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private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY)
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private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX)
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private val StaAddrModes = Set(Absolute, ZeroPage, ZeroPageX, AbsoluteX, IndexedY, IndexedX, AbsoluteY)
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private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage)
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// This optimization tends to prevent later Variable To Register Optimization,
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// so run this only after it's pretty sure V2RO won't happen any more
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@ -29,6 +35,54 @@ object LaterOptimizations {
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY), LDA, TYA),
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)
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private def a2x(line: AssemblyLine) = line.opcode match {
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case LDA => line.copy(opcode = LDX)
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case STA => line.copy(opcode = STX)
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case CMP => line.copy(opcode = CPX)
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case INC => line.copy(opcode = INX)
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case DEC => line.copy(opcode = DEX)
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}
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private def a2y(line: AssemblyLine) = line.opcode match {
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case LDA => line.copy(opcode = LDY)
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case STA => line.copy(opcode = STY)
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case CMP => line.copy(opcode = CPY)
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case INC => line.copy(opcode = INY)
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case DEC => line.copy(opcode = DEY)
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}
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private def x2a(line: AssemblyLine) = line.opcode match {
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case LDX => line.copy(opcode = LDA)
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case STX => line.copy(opcode = STA)
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case CPX => line.copy(opcode = CMP)
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case INX => line.copy(opcode = INC)
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case DEX => line.copy(opcode = DEC)
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}
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private def y2a(line: AssemblyLine) = line.opcode match {
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case LDY => line.copy(opcode = LDA)
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case STY => line.copy(opcode = STA)
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case CPY => line.copy(opcode = CMP)
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case INY => line.copy(opcode = INC)
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case DEY => line.copy(opcode = DEC)
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}
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val DoubleLoadToTwoRegistersWhenOneWillBeTrashed = new RuleBasedAssemblyOptimization("Double load to two registers when one will be trashed",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsX)).+ ~
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(Elidable & (HasOpcode(TAX) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2x)),
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsY)).+ ~
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(Elidable & (HasOpcode(TAY) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2y)),
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(STX) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
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(Elidable & (HasOpcode(TXA) | HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.X)) ~~> (_.init.map(x2a)),
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(STY) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
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(Elidable & (HasOpcode(TYA) | HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.Y)) ~~> (_.init.map(y2a)),
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)
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private def TwoDifferentLoadsWithNoFlagChangeInBetween(opcode1: Opcode.Value, middle: AssemblyLinePattern, opcode2: Opcode.Value, transferOpcode: Opcode.Value) = {
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(HasOpcode(opcode1) & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ChangesMemory) & middle & Not(HasOpcode(opcode2))).* ~
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@ -72,24 +126,17 @@ object LaterOptimizations {
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}
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//noinspection ZeroIndexToHead
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private def InterleavedImmediateLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & MatchImmediate(0)) ~
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(Elidable & HasOpcode(store) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(8)) ~
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(Elidable & HasOpcode(load) & MatchImmediate(1)) ~
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(Elidable & HasOpcode(store) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(9) & DontMatchParameter(8)) ~
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(Elidable & HasOpcode(load) & MatchImmediate(0)) ~~> { c =>
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List(c(2), c(3), c(0), c(1))
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}
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}
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//noinspection ZeroIndexToHead
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private def InterleavedAbsoluteLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~
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(Elidable & HasOpcode(store) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(8) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(load) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(1) & DontMatchParameter(8) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(store) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(9) & DontMatchParameter(8) & DontMatchParameter(1) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(load) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~~> { c =>
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List(c(2), c(3), c(0), c(1))
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private def InterleavedLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & MatchAddrMode(0) & MatchParameter(1)).capture(12) ~
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(Elidable & HasOpcode(store)).+.capture(10) ~
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(Elidable & HasOpcode(load) & MatchAddrMode(2) & MatchParameter(3) & DoesNotConcernMemoryAt(0, 1)).capture(13) ~
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(Elidable & HasOpcode(store) & DoesNotConcernMemoryAt(0, 1) & DoesNotConcernMemoryAt(2, 3)).+.capture(11) ~
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(Elidable & HasOpcode(load) & MatchAddrMode(0) & MatchParameter(1)) ~
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WhereNoMemoryAccessOverlapBetweenTwoLineLists(10, 11) ~~> { (_, ctx) =>
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List(ctx.get[List[AssemblyLine]](13),
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ctx.get[List[AssemblyLine]](11),
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ctx.get[List[AssemblyLine]](12),
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ctx.get[List[AssemblyLine]](10)).flatten
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}
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}
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@ -106,12 +153,9 @@ object LaterOptimizations {
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LAX, Not(ChangesA) & Not(ChangesX)),
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InterleavedImmediateLoads(LDA, STA),
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InterleavedImmediateLoads(LDX, STX),
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InterleavedImmediateLoads(LDY, STY),
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InterleavedAbsoluteLoads(LDA, STA),
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InterleavedAbsoluteLoads(LDX, STX),
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InterleavedAbsoluteLoads(LDY, STY),
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InterleavedLoads(LDA, STA),
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InterleavedLoads(LDX, STX),
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InterleavedLoads(LDY, STY),
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)
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private def pointlessLoadAfterStore(store: Opcode.Value, load: Opcode.Value, addrMode: AddrMode.Value, meantime: AssemblyLinePattern = Anything) = {
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@ -229,12 +273,6 @@ object LaterOptimizations {
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)
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private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY)
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private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX)
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private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY)
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private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX)
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private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage)
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private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = {
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val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes
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val stAddrModes = if (useX) StxAddrModes else StyAddrModes
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@ -195,6 +195,60 @@ trait AssemblyPattern {
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def capture(i: Int) = Capture(i, this)
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def captureLength(i: Int) = CaptureLength(i, this)
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protected def memoryAccessDoesntOverlap(a1: AddrMode.Value, p1: Constant, a2: AddrMode.Value, p2: Constant): Boolean = {
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import AddrMode._
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val badAddrModes = Set(IndexedX, IndexedY, ZeroPageIndirect, AbsoluteIndexedX)
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if (badAddrModes(a1) || badAddrModes(a2)) return false
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val goodAddrModes = Set(Implied, Immediate, Relative)
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if (goodAddrModes(a1) || goodAddrModes(a2)) return true
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def handleKnownDistance(distance: Short): Boolean = {
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val indexingAddrModes = Set(AbsoluteIndexedX, AbsoluteX, ZeroPageX, AbsoluteY, ZeroPageY)
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val a1Indexing = indexingAddrModes(a1)
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val a2Indexing = indexingAddrModes(a2)
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(a1Indexing, a2Indexing) match {
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case (false, false) => distance != 0
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case (true, false) => distance > 255 || distance < 0
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case (false, true) => distance > 0 || distance < -255
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case (true, true) => distance > 255 || distance < -255
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}
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}
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(p1.quickSimplify, p2.quickSimplify) match {
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case (NumericConstant(n1, _), NumericConstant(n2, _)) =>
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handleKnownDistance((n2 - n1).toShort)
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case (a, CompoundConstant(MathOperator.Plus, b, NumericConstant(distance, _))) if a.quickSimplify == b.quickSimplify =>
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handleKnownDistance(distance.toShort)
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case (CompoundConstant(MathOperator.Plus, a, NumericConstant(distance, _)), b) if a.quickSimplify == b.quickSimplify =>
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handleKnownDistance((-distance).toShort)
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case (a, CompoundConstant(MathOperator.Minus, b, NumericConstant(distance, _))) if a.quickSimplify == b.quickSimplify =>
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handleKnownDistance((-distance).toShort)
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case (CompoundConstant(MathOperator.Minus, a, NumericConstant(distance, _)), b) if a.quickSimplify == b.quickSimplify =>
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handleKnownDistance(distance.toShort)
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case (MemoryAddressConstant(_: ThingInMemory), NumericConstant(_, _)) =>
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true // TODO: ???
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case (NumericConstant(_, _), MemoryAddressConstant(_: ThingInMemory)) =>
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true // TODO: ???
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case (CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _)), NumericConstant(_, _)) =>
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true // TODO: ???
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case (NumericConstant(_, _), CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _))) =>
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true // TODO: ???
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case (MemoryAddressConstant(a: ThingInMemory), MemoryAddressConstant(b: ThingInMemory)) =>
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a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
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case (CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _)),
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MemoryAddressConstant(b: ThingInMemory)) =>
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a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
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case (MemoryAddressConstant(a: ThingInMemory),
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CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(b: ThingInMemory), NumericConstant(_, _))) =>
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a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
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case (CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _)),
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CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(b: ThingInMemory), NumericConstant(_, _))) =>
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a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
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case _ =>
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false
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}
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}
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}
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case class Capture(i: Int, pattern: AssemblyPattern) extends AssemblyPattern {
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@ -352,58 +406,20 @@ trait AssemblyLinePattern extends AssemblyPattern {
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def |(x: AssemblyLinePattern): AssemblyLinePattern = Either(this, x)
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def &(x: AssemblyLinePattern): AssemblyLinePattern = Both(this, x)
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protected def memoryAccessDoesntOverlap(a1: AddrMode.Value, p1: Constant, a2: AddrMode.Value, p2: Constant): Boolean = {
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import AddrMode._
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val badAddrModes = Set(IndexedX, IndexedY, ZeroPageIndirect, AbsoluteIndexedX)
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if (badAddrModes(a1) || badAddrModes(a2)) return false
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val goodAddrModes = Set(Implied, Immediate, Relative)
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if (goodAddrModes(a1) || goodAddrModes(a2)) return true
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def handleKnownDistance(distance: Short): Boolean = {
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val indexingAddrModes = Set(AbsoluteIndexedX, AbsoluteX, ZeroPageX, AbsoluteY, ZeroPageY)
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val a1Indexing = indexingAddrModes(a1)
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val a2Indexing = indexingAddrModes(a2)
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(a1Indexing, a2Indexing) match {
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case (false, false) => distance != 0
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case (true, false) => distance > 255 || distance < 0
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case (false, true) => distance > 0 || distance < -255
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case (true, true) => distance > 255 || distance < -255
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}
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}
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(p1.quickSimplify, p2.quickSimplify) match {
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case (NumericConstant(n1, _), NumericConstant(n2, _)) =>
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handleKnownDistance((n2 - n1).toShort)
|
||||
case (a, CompoundConstant(MathOperator.Plus, b, NumericConstant(distance, _))) if a.quickSimplify == b.quickSimplify =>
|
||||
handleKnownDistance(distance.toShort)
|
||||
case (CompoundConstant(MathOperator.Plus, a, NumericConstant(distance, _)), b) if a.quickSimplify == b.quickSimplify =>
|
||||
handleKnownDistance((-distance).toShort)
|
||||
case (a, CompoundConstant(MathOperator.Minus, b, NumericConstant(distance, _))) if a.quickSimplify == b.quickSimplify =>
|
||||
handleKnownDistance((-distance).toShort)
|
||||
case (CompoundConstant(MathOperator.Minus, a, NumericConstant(distance, _)), b) if a.quickSimplify == b.quickSimplify =>
|
||||
handleKnownDistance(distance.toShort)
|
||||
case (MemoryAddressConstant(a: ThingInMemory), MemoryAddressConstant(b: ThingInMemory)) =>
|
||||
a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
|
||||
case (CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _)),
|
||||
MemoryAddressConstant(b: ThingInMemory)) =>
|
||||
a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
|
||||
case (MemoryAddressConstant(a: ThingInMemory),
|
||||
CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(b: ThingInMemory), NumericConstant(_, _))) =>
|
||||
a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
|
||||
case (CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(a: ThingInMemory), NumericConstant(_, _)),
|
||||
CompoundConstant(MathOperator.Plus | MathOperator.Minus, MemoryAddressConstant(b: ThingInMemory), NumericConstant(_, _))) =>
|
||||
a.name.takeWhile(_ != '.') != b.name.takeWhile(_ != '.') // TODO: ???
|
||||
case _ =>
|
||||
false
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait TrivialAssemblyLinePattern extends AssemblyLinePattern with (AssemblyLine => Boolean) {
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean = this (line)
|
||||
}
|
||||
|
||||
case class WhereNoMemoryAccessOverlapBetweenTwoLineLists(ix1: Int, ix2: Int) extends AssemblyPattern {
|
||||
override def matchTo(ctx: AssemblyMatchingContext, code: List[(FlowInfo, AssemblyLine)]): Option[List[(FlowInfo, AssemblyLine)]] = {
|
||||
val s1s = ctx.get[List[AssemblyLine]](ix1)
|
||||
val s2s = ctx.get[List[AssemblyLine]](ix2)
|
||||
if (s1s.forall(s1 => s2s.forall(s2 => memoryAccessDoesntOverlap(s1.addrMode, s1.parameter, s2.addrMode, s2.parameter)))) Some(code) else None
|
||||
}
|
||||
}
|
||||
|
||||
//noinspection LanguageFeature
|
||||
object AssemblyLinePattern {
|
||||
implicit def __implicitOpcodeIn(ops: Set[Opcode.Value]): AssemblyLinePattern = HasOpcodeIn(ops)
|
||||
|
||||
@ -156,6 +156,23 @@ class ArraySuite extends FunSuite with Matchers {
|
||||
|
||||
}
|
||||
|
||||
test("Pointer indexing test") {
|
||||
EmuBenchmarkRun(
|
||||
"""
|
||||
| array output [4] @$c000
|
||||
| pointer a
|
||||
| byte i
|
||||
| void main () {
|
||||
| setup()
|
||||
| a[i + 1] = 55
|
||||
| }
|
||||
| void setup() {
|
||||
| a = output.addr
|
||||
| i = 2
|
||||
| }
|
||||
""".stripMargin)(_.readByte(0xc003) should equal(55))
|
||||
}
|
||||
|
||||
test("Syntax") {
|
||||
EmuUnoptimizedRun(
|
||||
"""
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user