mirror of https://github.com/KarolS/millfork.git
Improvements for 65CE02 assembly (fixes #116)
This commit is contained in:
Karol Stasiak
parent
faf97cee1f
commit
7f0def54bc
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@ -693,6 +693,8 @@ case class AssemblyLine(opcode: Opcode.Value, addrMode: AddrMode.Value, var para
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parameter match {
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case StructureConstant(_, List(a,b)) => s" $opcode $a,$b"
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}
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} else if (addrMode == LongRelative && opcode != BSR) { // BSR on Hudson is always 8-bit short, and on 65CE02 it's always 16-bit
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s" L$opcode ${AddrMode.addrModeToString(addrMode, parameter.toString)}"
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} else if (addrMode == ImmediateWithAbsolute || addrMode == ImmediateWithZeroPage) {
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parameter match {
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case StructureConstant(_, List(a,b)) => s" $opcode #$a,$b"
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@ -180,20 +180,31 @@ object Opcode extends Enumeration {
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case "AXA" => AHX
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case "AXS" => SBX // could mean SAX
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case "BCC" => BCC
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case "LBCC" => BCC
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case "BCS" => BCS
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case "LBCS" => BCS
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case "BEQ" => BEQ
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case "LBEQ" => BEQ
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case "BIT" => BIT
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case "BMI" => BMI
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case "LBMI" => BMI
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case "BNE" => BNE
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case "LBNE" => BNE
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case "BPL" => BPL
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case "LBPL" => BPL
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case "BRA" => BRA
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case "LBRA" => BRA
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case "BRK" => BRK
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case "BRL" => BRL
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case "BSR" => BSR
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case "LBSR" => BSR
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case "BVC" => BVC
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case "LBVC" => BVC
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case "BVS" => BVS
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case "LBVS" => BVS
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case "CLC" => CLC
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case "CLD" => CLD
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case "CLE" => CLE
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case "CLI" => CLI
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case "CLV" => CLV
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case "CLX" => CLX
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@ -232,6 +243,7 @@ object Opcode extends Enumeration {
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case "LSE" => SRE
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case "LSR" => LSR
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case "LXA" => LXA
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case "MAP" => MAP
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case "NEG" => NEG
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case "NOP" => NOP
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case "OAL" => LXA
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@ -247,17 +259,19 @@ object Opcode extends Enumeration {
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case "PHW" => PHW
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case "PHX" => PHX
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case "PHY" => PHY
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case "PHZ" => PHZ
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case "PLA" => PLA
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case "PLB" => PLB
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case "PLD" => PLD
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case "PLP" => PLP
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case "PLX" => PLX
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case "PLY" => PLY
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case "PLZ" => PLZ
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case "REP" => REP
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case "RLA" => RLA
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case "ROL" => ROL
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case "ROR" => ROR
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case "ROW" => ROR_W // TODO: is this correct?
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case "ROW" => ROL_W
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case "RRA" => RRA
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case "RTI" => RTI
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case "RTL" => RTL
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@ -268,6 +282,7 @@ object Opcode extends Enumeration {
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case "SBX" => SBX
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case "SEC" => SEC
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case "SED" => SED
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case "SEE" => SEE
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case "SEI" => SEI
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case "SEP" => SEP
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case "SET" => SET
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@ -164,14 +164,14 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
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val c: Constant = compileParameterForAssemblyStatement(env, o, x)
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val actualAddrMode = a match {
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case Absolute if OpcodeClasses.ShortBranching(o) => Relative
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case Absolute if (o == ROR_W || o == ASL_W) && ctx.options.flag(CompilationFlag.Emit65CE02Opcodes) =>
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case Absolute if (o == ROL_W || o == ASL_W) && ctx.options.flag(CompilationFlag.Emit65CE02Opcodes) =>
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Absolute
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case Absolute if OpcodeClasses.SupportsZeropage(o) && c.fitsProvablyIntoByte => ZeroPage
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case ImmediateWithAbsolute if (c match {
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case StructureConstant(_, List(a, b)) => b.fitsProvablyIntoByte
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}) => ImmediateWithZeroPage
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case IndexedX if o == JMP => AbsoluteIndexedX
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case Indirect if o != JMP => IndexedZ
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case IndexedX if o == JMP || o == JSR => AbsoluteIndexedX
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case Indirect if o != JMP && o != JSR => IndexedZ
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case _ => a
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}
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List(AssemblyLine(o, actualAddrMode, c, e)) -> Nil
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@ -64,6 +64,11 @@ class MosAssembler(program: Program,
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writeByte(bank, index, MosAssembler.opcodeFor(op, am, options))
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writeWord(bank, index + 1, param)
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index + 3
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case AssemblyLine0(op, am@LongRelative, param) =>
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writeByte(bank, index, MosAssembler.opcodeFor(op, am, options))
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// TODO:
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writeWord(bank, index + 1, param - (index + 3))
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index + 3
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case AssemblyLine0(op, am@(LongAbsolute | LongAbsoluteX | LongIndirect), param) =>
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writeByte(bank, index, MosAssembler.opcodeFor(op, am, options))
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writeWord(bank, index + 1, param)
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@ -720,8 +725,7 @@ object MosAssembler {
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ce(DEC_W, ZeroPage, 0xC3)
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ce(INC_W, ZeroPage, 0xE3)
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ce(ASL_W, Absolute, 0xCB)
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// TODO: or is it ROL_W?
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ce(ROR_W, Absolute, 0xEB)
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ce(ROL_W, Absolute, 0xEB)
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ce(ASR, Implied, 0x43)
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ce(ASR, ZeroPage, 0x44)
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ce(ASR, ZeroPageX, 0x54)
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@ -738,10 +742,26 @@ object MosAssembler {
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ce(PHW, Absolute, 0xFC)
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ce(PHZ, Implied, 0xDB)
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ce(PLZ, Implied, 0xFB)
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// ce(CLE, Implied, )
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// ce(SEE, Implied, )
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// ce(BSR, , )
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ce(JSR, Indirect, 0x22)
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ce(JSR, AbsoluteIndexedX, 0x23)
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ce(CLE, Implied, 0x02)
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ce(SEE, Implied, 0x03)
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ce(NEG, Implied, 0x42)
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ce(MAP, Implied, 0x5C)
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ce(LDA, IndexedSY, 0xE2)
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ce(STA, IndexedSY, 0x82)
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ce(BSR, LongRelative, 0x63)
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ce(BRA, LongRelative, 0x83)
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ce(BPL, LongRelative, 0x13)
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ce(BMI, LongRelative, 0x33)
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ce(BVC, LongRelative, 0x53)
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ce(BVS, LongRelative, 0x73)
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ce(BCC, LongRelative, 0x93)
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ce(BCS, LongRelative, 0xb3)
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ce(BNE, LongRelative, 0xd3)
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ce(BEQ, LongRelative, 0xf3)
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hu(BSR, Relative, 0x44)
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hu(CLY, Implied, 0xC2)
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hu(CLX, Implied, 0x82)
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hu(CLA, Implied, 0x62)
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@ -816,6 +836,8 @@ object MosAssembler {
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em(XBA, Implied, 0xEB)
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em(TXY, Implied, 0x9B)
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em(TYX, Implied, 0xBB)
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em(JSR, LongAbsolute, 0x22)
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em(JSR, AbsoluteIndexedX, 0xFC)
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na(RTL, Implied, 0x6B)
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@ -24,7 +24,11 @@ case class MosParser(filename: String, input: String, currentDirectory: String,
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// def zeropageAddrModeHint: P[Option[Boolean]] = Pass
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val asmOpcode: P[Opcode.Value] = (position() ~ mosOpcodeLetter.rep(exactly = 3).! ~ octalDigit.?.! ~ ("_W" | "_w").?.!).map { case (p, bitNo, suffix, o) => Opcode.lookup(o + bitNo + suffix, Some(p), log) }
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val asmOpcode: P[(Boolean, Opcode.Value)] = (position() ~
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(("l" | "L") ~ ("b" | "B") ~ mosOpcodeLetter.rep(exactly = 2) |
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(mosOpcodeLetter.rep(exactly = 3).! ~ octalDigit.?.! ~ ("_W" | "_w").?)).!).map { case (p, o) =>
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o.toLowerCase.startsWith("lb") -> Opcode.lookup(o, Some(p), log)
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}
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private val commaX = HWS ~ "," ~ HWS ~ ("X" | "x") ~ HWS
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private val commaY = HWS ~ "," ~ HWS ~ ("Y" | "y") ~ HWS
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@ -77,8 +81,8 @@ case class MosParser(filename: String, input: String, currentDirectory: String,
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import Opcode._
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for {
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elid <- !"}" ~ elidable
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position <- position("assembly statement")
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op <- asmOpcode ~/ Pass
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pos <- position("assembly statement")
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(longrelative, op) <- asmOpcode ~/ Pass
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param <- op match {
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case op if OpcodeClasses.SingleBitBranch(op) =>
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(HWS ~ asmExpression ~ HWS ~ "," ~/ HWS ~ asmExpression).map{ x =>
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@ -102,12 +106,23 @@ case class MosParser(filename: String, input: String, currentDirectory: String,
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case (Opcode.ASR, AddrMode.Absolute) => MosAssemblyStatement(Opcode.ASR, AddrMode.ZeroPage, param._2, elid)
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case (Opcode.ASR, AddrMode.AbsoluteX) => MosAssemblyStatement(Opcode.ASR, AddrMode.ZeroPageX, param._2, elid)
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case (Opcode.SBX, _) => MosAssemblyStatement(Opcode.SAX, param._1, param._2, elid)
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case (Opcode.BSR, AddrMode.Absolute) if options.flag(CompilationFlag.Emit65CE02Opcodes) || longrelative =>
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MosAssemblyStatement(Opcode.BSR, AddrMode.LongRelative, param._2, elid)
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case (Opcode.BSR, AddrMode.Absolute) if options.flag(CompilationFlag.EmitHudsonOpcodes) =>
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MosAssemblyStatement(Opcode.BSR, AddrMode.Relative, param._2, elid)
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case (Opcode.PHW, AddrMode.Immediate) => MosAssemblyStatement(Opcode.PHW, AddrMode.WordImmediate, param._2, elid)
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case (op, AddrMode.AbsoluteX)
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if (op == INC_W || op == DEC_W) && !options.flag(CompilationFlag.EmitNative65816Opcodes) =>
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MosAssemblyStatement(op, AddrMode.ZeroPageX, param._2, elid)
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case (_, AddrMode.Absolute) if OpcodeClasses.ShortBranching(op) =>
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MosAssemblyStatement(op, if (longrelative) AddrMode.LongRelative else AddrMode.Relative, param._2, elid)
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case (_, AddrMode.ZeroPageX) if !OpcodeClasses.SupportsZeroPageX(op) => MosAssemblyStatement(op, AddrMode.AbsoluteX, param._2, elid)
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case (_, AddrMode.ZeroPageY) if !OpcodeClasses.SupportsZeroPageY(op) => MosAssemblyStatement(op, AddrMode.AbsoluteY, param._2, elid)
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case (_, AddrMode.Absolute) if OpcodeClasses.SingleBit(op) => MosAssemblyStatement(op, AddrMode.ZeroPage, param._2, elid)
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case (_, AddrMode.IndexedX) if op == Opcode.JMP || op == Opcode.JSR => MosAssemblyStatement(op, AddrMode.AbsoluteIndexedX, param._2, elid)
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case (_, AddrMode.Indirect) if op != Opcode.JMP && op != Opcode.JSR => MosAssemblyStatement(op, AddrMode.IndexedZ, param._2, elid)
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case _ => MosAssemblyStatement(op, param._1, param._2, elid)
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}).pos(position)
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}).pos(pos)
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}
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}
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@ -572,4 +572,91 @@ class AssemblySuite extends FunSuite with Matchers with AppendedClues {
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|""".stripMargin)
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m.readByte(0xc000) should equal(0x12)
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}
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test("65CE02 opcodes") {
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EmuUnoptimizedCrossPlatformRun(Cpu.CE02)(
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"""
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|byte output @$c000
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|void stuff() {
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| output = 42
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|}
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|void main() {
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| word p
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| p = stuff.addr
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| asm {
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| jsr (p)
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| }
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| return
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| asm {
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| bsr stuff
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| see
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| cle
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| ldz #$a3
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| ldz $abab
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| ldz $bbbb,x
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| stz $64
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| stz $74,x
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| stz $9c9c
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| stz $9e9e,x
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| asr
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| asr $44
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| asr $54,x
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| asw $cbcb
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| row $ebeb
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| dew $c3
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| inw $e3
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| neg
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| dec
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| inc
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| dez
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| inz
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| tab
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| tba
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| taz
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| tza
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| tsy
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| tys
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| phw #$f4f4
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| phw $fcfc
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| phx
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| phy
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| phz
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| plz
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| ply
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| plx
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| .here: bra .here
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| bbr0 $0F, .here
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| bbs0 $8F, .here
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| jsr ($2323,x)
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| jmp ($7c7c,x)
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| rmb0 $07
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| smb0 $87
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| ora ($12),z
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| and ($32),z
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| eor ($52),z
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| adc ($72),z
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| sta ($92),z
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| lda ($b2),z
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| cmp ($d2),z
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| sbc ($f2),z
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| lda ($e2,s),y
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| sta ($82,s),y
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| map
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| [for x,0,until,300 [0]]
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| lbra .here
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| lbeq .here
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| lbcc .here
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| lbcs .here
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| lbvs .here
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| lbvc .here
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| lbmi .here
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| lbpl .here
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| }
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|}
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|""".stripMargin) { m =>
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m.readByte(0xc000) should equal(42)
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}
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}
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}
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@ -10,6 +10,7 @@ object EmuUnoptimizedCrossPlatformRun {
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def apply(platforms: Cpu.Value*)(source: String)(verifier: MemoryBank => Unit): Unit = {
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val (_, mm) = if (platforms.contains(Cpu.Mos) || platforms.contains(Cpu.StrictMos)) EmuUnoptimizedRun.apply2(source) else Timings(-1, -1) -> null
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val (_, mc) = if (platforms.contains(Cpu.Cmos)) EmuUnoptimizedCmosRun.apply2(source) else Timings(-1, -1) -> null
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val (_, me) = if (platforms.contains(Cpu.CE02)) EmuUnoptimizedCE02Run.apply2(source) else Timings(-1, -1) -> null
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val (_, ma) = if (platforms.contains(Cpu.Sixteen)) EmuUnoptimizedNative65816Run.apply2(source) else Timings(-1, -1) -> null
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val (_, mn) = if (platforms.contains(Cpu.Ricoh)) EmuUnoptimizedRicohRun.apply2(source) else Timings(-1, -1) -> null
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val (_, mz) = if (platforms.contains(Cpu.Z80)) EmuUnoptimizedZ80Run.apply2(source) else Timings(-1, -1) -> null
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@ -33,6 +34,10 @@ object EmuUnoptimizedCrossPlatformRun {
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println(f"Running 65C02")
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verifier(mc)
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}
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if (Settings.enableCE02Tests && platforms.contains(Cpu.CE02)) {
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println(f"Running 65CE02")
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verifier(me)
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}
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if (Settings.enableZ80Tests && platforms.contains(Cpu.Z80)) {
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println(f"Running Z80")
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verifier(mz)
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@ -12,6 +12,8 @@ object EmuUnoptimizedRicohRun extends EmuRun(Cpu.Ricoh, Nil, Nil)
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object EmuUnoptimizedCmosRun extends EmuRun(Cpu.Cmos, Nil, Nil)
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object EmuUnoptimizedCE02Run extends EmuRun(Cpu.CE02, Nil, Nil)
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object EmuUnoptimizedHudsonRun extends EmuRun(Cpu.HuC6280, Nil, Nil)
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object EmuUnoptimizedNative65816Run extends EmuRun(Cpu.Sixteen, Nil, Nil) {
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@ -28,6 +28,12 @@ object Settings {
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*/
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val enableWdc85816Tests: Boolean = false
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/**
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* Should the 65CE02 tests be enabled?
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* There is no emulator for 65CE02 right now.
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*/
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val enableCE02Tests: Boolean = false
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/**
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* Should the Ricoh tests be enabled?
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* Ricoh tests:
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