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Optimize the zp_reg module

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This commit is contained in:
Karol Stasiak 2019-06-28 16:27:35 +02:00
parent 95249da671
commit 7f28a6b10f
1 changed files with 21 additions and 21 deletions
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42
include/zp_reg.mfk
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@ -8,11 +8,11 @@ noinline asm byte __mul_u8u8u8() {
? JMP __mul_u8u8u8_start ? JMP __mul_u8u8u8_start
__mul_u8u8u8_add: __mul_u8u8u8_add:
? CLC ? CLC
? ADC __reg.lo ? ADC lo(__reg)
__mul_u8u8u8_loop: __mul_u8u8u8_loop:
? ASL __reg.lo ? ASL lo(__reg)
__mul_u8u8u8_start: __mul_u8u8u8_start:
? LSR __reg.hi ? LSR lo(__reg+1)
? BCS __mul_u8u8u8_add ? BCS __mul_u8u8u8_add
? BNE __mul_u8u8u8_loop ? BNE __mul_u8u8u8_loop
? RTS ? RTS
@ -25,21 +25,21 @@ noinline asm byte __mod_u8u8u8u8() {
? LDX #7 ? LDX #7
? CLC ? CLC
__divmod_u8u8u8u8_start: __divmod_u8u8u8u8_start:
? ROL __reg ? ROL lo(__reg)
? ROL ? ROL
? CMP __reg+1 ? CMP lo(__reg+1)
? BCC __divmod_u8u8u8u8_skip ? BCC __divmod_u8u8u8u8_skip
? SBC __reg+1 ? SBC lo(__reg+1)
__divmod_u8u8u8u8_skip: __divmod_u8u8u8u8_skip:
? DEX ? DEX
? BPL __divmod_u8u8u8u8_start ? BPL __divmod_u8u8u8u8_start
? ROL __reg ? ROL lo(__reg)
? RTS ? RTS
} }
asm byte __div_u8u8u8u8() { asm byte __div_u8u8u8u8() {
? JSR __mod_u8u8u8u8 ? JSR __mod_u8u8u8u8
? LDA __reg ? LDA lo(__reg)
? RTS ? RTS
} }
@ -51,17 +51,17 @@ noinline asm word __mul_u16u8u16() {
? JMP __mul_u16u8u16_start ? JMP __mul_u16u8u16_start
__mul_u16u8u16_add: __mul_u16u8u16_add:
? CLC ? CLC
? ADC __reg ? ADC lo(__reg)
? TAY ? TAY
? TXA ? TXA
? ADC __reg + 1 ? ADC lo(__reg+1)
? TAX ? TAX
? TYA ? TYA
__mul_u16u8u16_loop: __mul_u16u8u16_loop:
? ASL __reg ? ASL lo(__reg)
? ROL __reg + 1 ? ROL lo(__reg+1)
__mul_u16u8u16_start: __mul_u16u8u16_start:
? LSR __reg + 2 ? LSR lo(__reg+2)
? BCS __mul_u16u8u16_add ? BCS __mul_u16u8u16_add
? BNE __mul_u16u8u16_loop ? BNE __mul_u16u8u16_loop
? RTS ? RTS
@ -74,24 +74,24 @@ noinline asm byte __mod_u16u8u16u8() {
? LDX #15 ? LDX #15
? CLC ? CLC
__divmod_u16u8u16u8_start: __divmod_u16u8u16u8_start:
? ROL __reg ? ROL lo(__reg)
? ROL __reg+1 ? ROL lo(__reg+1)
? ROL ? ROL
? CMP __reg+2 ? CMP lo(__reg+2)
? BCC __divmod_u16u8u16u8_skip ? BCC __divmod_u16u8u16u8_skip
? SBC __reg+2 ? SBC lo(__reg+2)
__divmod_u16u8u16u8_skip: __divmod_u16u8u16u8_skip:
? DEX ? DEX
? BPL __divmod_u16u8u16u8_start ? BPL __divmod_u16u8u16u8_start
? ROL __reg ? ROL lo(__reg)
? ROL __reg+1 ? ROL lo(__reg+1)
? RTS ? RTS
} }
asm word __div_u16u8u16u8() { asm word __div_u16u8u16u8() {
? JSR __mod_u16u8u16u8 ? JSR __mod_u16u8u16u8
? LDA __reg ? LDA lo(__reg)
? LDX __reg+1 ? LDX lo(__reg+1)
? RTS ? RTS
} }