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Z80: Improve optimizations
This commit is contained in:
Karol Stasiak
parent
72f8806c54
commit
7fe32ca564
@ -36,7 +36,7 @@ object AlwaysGoodI80Optimizations {
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List(ZRegister.B, ZRegister.C, ZRegister.D, ZRegister.E, ZRegister.H, ZRegister.L, ZRegister.MEM_HL).map(f))
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val UsingKnownValueFromAnotherRegister = new RuleBasedAssemblyOptimization("Using known value from another register",
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needsFlowInfo = FlowInfoRequirement.ForwardFlow,
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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for7Registers(register =>
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(Elidable & IsRegular8BitLoadFrom(register) & MatchRegister(register, 0)) ~~> ((code, ctx) =>
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code.map(x => x.copy(
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@ -71,6 +71,23 @@ object AlwaysGoodI80Optimizations {
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registers = OneRegister(ZRegister.IMM_8)
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))
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),
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MultipleAssemblyRules(for {
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(useful, useless, both, extractUseful) <- Seq[(ZRegister.Value, ZRegister.Value, ZRegister.Value, Constant => Constant)](
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(B, C, BC, _.hiByte),
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(C, B, BC, _.loByte),
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(D, E, DE, _.hiByte),
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(E, D, DE, _.loByte),
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(H, L, HL, _.hiByte),
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(L, H, HL, _.loByte)
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)
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} yield {
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(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(both, IMM_16)) & MatchParameter(0)) ~
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(Linear & Not(Concerns(useful)) & Not(Concerns(useless))).* ~
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(Elidable & HasOpcodeIn(Set(ADD, ADC, SUB, SBC, XOR, OR, AND, CP)) & HasRegisterParam(useful) & DoesntMatterWhatItDoesWith(useless)) ~~> { (code, ctx) =>
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code.tail.init :+ code.last.copy(registers = OneRegister(IMM_8), parameter = extractUseful(ctx.get[Constant](0)))
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}
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}),
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)
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val ReloadingKnownValueFromMemory = new RuleBasedAssemblyOptimization("Reloading known value from memory",
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@ -296,6 +313,13 @@ object AlwaysGoodI80Optimizations {
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(HasOpcode(LD) & MatchSourceRealRegister(0) & MatchTargetRealRegister(1)) ~
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(Linear & Not(ChangesMatchedRegister(0)) & Not(ChangesMatchedRegister(1))).* ~
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(Elidable & HasOpcode(LD) & MatchSourceRealRegister(1) & MatchTargetRealRegister(0)) ~~> (_.init),
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// 68
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(Elidable & HasOpcode(LD) & Match8BitImmediate(1) & MatchTargetRegisterAndOffset(2)) ~
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Where(ctx => ctx.get[RegisterAndOffset](2).isOneOfSeven) ~
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(Elidable & HasOpcode(LD) & MatchSourceRegisterAndOffset(2) & MatchTargetRealRegister(3) & DoesntMatterWhatItDoesWithMatchedRegisterOffset(2)) ~~> {(code, ctx) =>
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List(code.head.copy(registers = TwoRegisters(ctx.get[ZRegister.Value](3), IMM_8)))
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},
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)
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val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",
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@ -259,6 +259,10 @@ object CoarseFlowAnalyzer {
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currentStatus = currentStatus.setRegister(t, SingleStatus(value.toInt))
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case ZLine0(LD_16, TwoRegisters(ZRegister.HL, ZRegister.IMM_16), xx) =>
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currentStatus = currentStatus.setHL(SingleStatus(xx))
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case ZLine0(LD_16, TwoRegisters(ZRegister.DE, ZRegister.IMM_16), xx) if xx.isProvablyDivisibleBy256 =>
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currentStatus = currentStatus.copy(d = AnyStatus, e = Status.SingleZero)
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case ZLine0(LD_16, TwoRegisters(ZRegister.BC, ZRegister.IMM_16), xx) if xx.isProvablyDivisibleBy256 =>
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currentStatus = currentStatus.copy(b = AnyStatus, c = Status.SingleZero)
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case ZLine0(LD, TwoRegisters(ZRegister.A, ZRegister.I | ZRegister.R), _) =>
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currentStatus = currentStatus.copy(a = AnyStatus, zf = AnyStatus, sf = AnyStatus, pf = AnyStatus, hf = AnyStatus, nf = AnyStatus)
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case ZLine0(LD, TwoRegisters(t, ZRegister.IMM_8), NumericConstant(value, _)) =>
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@ -145,8 +145,8 @@ case class CpuImportance(a: Importance = UnknownImportance,
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case ZRegister.E => this.copy(e = Unimportant)
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case ZRegister.DE => this.copy(d = Unimportant, e = Unimportant)
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case ZRegister.MEM_DE => this.copy(d = Important, e = Important)
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case ZRegister.H => this.copy(h = Unimportant)
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case ZRegister.L => this.copy(l = Unimportant)
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case ZRegister.H => this.copy(h = Unimportant, hlNumeric = this.l)
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case ZRegister.L => this.copy(l = Unimportant, hlNumeric = this.h)
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case ZRegister.HL => this.copy(h = Unimportant, l = Unimportant, hlNumeric = Unimportant)
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case ZRegister.MEM_HL => this.copy(h = Important, l = Important)
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case ZRegister.IXH => this.copy(ixh = Unimportant)
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@ -469,7 +469,7 @@ object ReverseFlowAnalyzer {
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currentImportance = currentImportance.copy(cf = Unimportant, hf = Unimportant, nf = Unimportant)
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case ZLine0(LD_HLSP, _, _) =>
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currentImportance = currentImportance.copy(h = Unimportant, l = Unimportant)
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currentImportance = currentImportance.copy(h = Unimportant, l = Unimportant, hlNumeric = Unimportant)
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case ZLine0(RIM, _, _) =>
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currentImportance = currentImportance.copy(a = Unimportant)
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@ -559,12 +559,18 @@ case class MatchImmediate(i: Int) extends AssemblyLinePattern {
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}
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case class RegisterAndOffset(register: ZRegister.Value, offset: Int) {
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def toOneRegister: ZRegisters = register match {
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case ZRegister.MEM_IX_D | ZRegister.MEM_IY_D => OneRegisterOffset(register, offset)
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case _ =>
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if (offset != 0) ???
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OneRegister(register)
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}
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def isOneOfSeven: Boolean = register match {
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case ZRegister.A | ZRegister.B | ZRegister.C | ZRegister.D | ZRegister.E | ZRegister.H | ZRegister.L => true
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case _ => false
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}
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}
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case class MatchSourceRegisterAndOffset(i: Int) extends AssemblyLinePattern {
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@ -745,6 +751,21 @@ case class DoesntMatterWhatItDoesWith(registers: ZRegister.Value*) extends Assem
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override def hitRate: Double = 0.058
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}
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case class DoesntMatterWhatItDoesWithMatchedRegisterOffset(i: Int) extends AssemblyLinePattern {
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override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
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FlowInfoRequirement.assertBackward(needsFlowInfo)
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override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean = {
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val ro = ctx.get[RegisterAndOffset](i)
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ro.isOneOfSeven && flowInfo.importanceAfter.getRegister(ro.register) != Important
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}
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override def toString: String = "[¯\\_(ツ)_/¯:" + i + "]"
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override def hitRate: Double = 0.058
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}
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case object DoesntMatterWhatItDoesWithFlags extends AssemblyLinePattern {
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override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
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@ -18,7 +18,10 @@ class VariableStatus(val paramVariables: Set[String],
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val localVariables: List[Variable],
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val variablesWithLifetimes: List[(Variable, Range)],
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val variablesWithLifetimesMap: Map[String, Range],
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val codeWithFlow: List[(FlowInfo, ZLine)])
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val codeWithFlow: List[(FlowInfo, ZLine)]) {
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override def toString = s"VariableStatus(paramVariables=$paramVariables, stillUsedVariables=$stillUsedVariables, variablesWithAddressesTaken=$variablesWithAddressesTaken, localVariables=$localVariables, variablesWithLifetimesMap=$variablesWithLifetimesMap)"
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}
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object VariableStatus {
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def apply(f: NormalFunction, code: List[ZLine], optimizationContext: OptimizationContext, typFilter: Type => Boolean): Option[VariableStatus] = {
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@ -49,20 +52,26 @@ object VariableStatus {
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case _ => None
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}.toSet
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val variablesWithAddressesTaken = code.zipWithIndex.flatMap {
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case (ZLine0(_, _, SubbyteConstant(MemoryAddressConstant(th), _)), _) =>
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case (l@ZLine0(_, _, SubbyteConstant(MemoryAddressConstant(th), _)), _) =>
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// println(th.name -> l)
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Some(th.name)
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case (ZLine0(_, _, SubbyteConstant(CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(_, _)), _)), _) =>
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case (l@ZLine0(_, _, SubbyteConstant(CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(_, _)), _)), _) =>
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// println(th.name -> l)
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Some(th.name)
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case (ZLine0(_,
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case (l@ZLine0(_,
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TwoRegisters(ZRegister.MEM_HL, _) | TwoRegisters(_, ZRegister.MEM_HL) | OneRegister(ZRegister.MEM_HL),
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_), i) =>
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flow(i)._1.statusBefore.hl match {
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case SingleStatus(MemoryAddressConstant(th)) =>
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if (flow(i)._1.importanceAfter.hlNumeric != Unimportant) Some(th.name)
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else None
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if (flow(i)._1.importanceAfter.hlNumeric != Unimportant) {
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// println(th.name -> l)
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Some(th.name)
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}else None
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case SingleStatus(CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(_, _))) =>
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if (flow(i)._1.importanceAfter.hlNumeric != Unimportant) Some(th.name)
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else None
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if (flow(i)._1.importanceAfter.hlNumeric != Unimportant) {
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// println(th.name -> l)
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Some(th.name)
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} else None
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case _ => None // TODO: ???
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}
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case _ => None
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@ -2,7 +2,7 @@ package millfork.assembly.z80.opt
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import millfork.{CompilationFlag, NonOverlappingIntervals}
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import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext}
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import millfork.assembly.z80.{TwoRegisters, ZFlag, ZLine, ZLine0}
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import millfork.assembly.z80.{OneRegister, TwoRegisters, ZFlag, ZLine, ZLine0}
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import millfork.env._
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import millfork.error.ConsoleLogger
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import millfork.node.ZRegister
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@ -263,6 +263,22 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), Elidability.Elidable, _)) :: xs if th.name == vname =>
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canBeInlined(vname, synced = true, target, xs).map(add(target == BC, CyclesAndBytes(16, 3), CyclesAndBytes(8, 1)))
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case (_, ZLine(OR, OneRegister(A), _, Elidability.Elidable, _)) ::
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(f, ZLine(SBC_16, TwoRegisters(HL, BC | DE), _, Elidability.Elidable, _)) :: xs if target == HL =>
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val i = f.importanceAfter
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if (i.h == Unimportant &&
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i.l == Unimportant &&
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i.a == Unimportant &&
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i.hf == Unimportant &&
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i.nf == Unimportant &&
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i.pf == Unimportant &&
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i.sf == Unimportant &&
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i.zf == Unimportant) {
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canBeInlined(vname, synced = true, target, xs).map(add(CyclesAndBytes(3, -1)))
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} else {
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None
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}
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case (_, x) :: (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, t), MemoryAddressConstant(th), Elidability.Elidable, _)) :: xs
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if th.name == vname && t == target && x.changesRegister(t) =>
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canBeInlined(vname, synced = true, target, xs).map(add(CyclesAndBytes(16, 3)))
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@ -300,6 +316,24 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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// if (code.nonEmpty) println(code.head)
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code match {
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case (_, ZLine(OR, OneRegister(A), _, _, _)) ::
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(_, l@ZLine(SBC_16, TwoRegisters(HL, BC), _, _, _)) ::
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xs if hl != "" =>
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tailcall(inlineVars(hl, bc, de, xs)).map(
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ZLine.ld8(A, L).pos(l.source) ::
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ZLine.register(SUB, C).pos(l.source) ::
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ZLine.ld8(A, H).pos(l.source) ::
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ZLine.register(SBC, B).pos(l.source) :: _)
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case (_, ZLine(OR, OneRegister(A), _, _, _)) ::
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(_, l@ZLine(SBC_16, TwoRegisters(HL, DE), _, _, _)) ::
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xs if hl != "" =>
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tailcall(inlineVars(hl, bc, de, xs)).map(
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ZLine.ld8(A, L).pos(l.source) ::
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ZLine.register(SUB, E).pos(l.source) ::
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ZLine.ld8(A, H).pos(l.source) ::
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ZLine.register(SBC, D).pos(l.source) :: _)
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case (_, load@ZLine(LD_16, TwoRegisters(BC, IMM_16), _, _, s1)) ::
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(f, add@ZLine(ADD_16, TwoRegisters(HL, BC), _, _, s2)) ::
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xs if bc != "" =>
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