mirror of
https://github.com/KarolS/millfork.git
synced 2024-12-22 16:31:02 +00:00
Bugfixes for undocumented optimizations and a better test suite for them
This commit is contained in:
Karol Stasiak
parent
d95d74104f
commit
810ac4f00e
@ -15,9 +15,7 @@ object UndocumentedOptimizations {
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val counter = new AtomicInteger(30000)
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def getNextLabel(prefix: String) = f".${prefix}%s__${counter.getAndIncrement()}%05d"
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// TODO: test these
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def getNextLabel(prefix: String) = f".$prefix%s__${counter.getAndIncrement()}%05d"
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private val LaxAddrModeRestriction = Not(HasAddrModeIn(Set(AbsoluteX, ZeroPageX, IndexedX, Immediate)))
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@ -72,23 +70,21 @@ object UndocumentedOptimizations {
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val SaxModes: Set[AddrMode.Value] = Set(ZeroPage, IndexedX, ZeroPageY, Absolute)
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val UseSax = new RuleBasedAssemblyOptimization("Using undocumented instruction SAX",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ConcernsA) & Not(ConcernsX)).?.capture(10) ~
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.X)) ~
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(Linear & Not(ConcernsA) & Not(ConcernsX) & DoesntChangeMemoryAt(0, 1)).*.capture(10) ~
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(HasOpcode(AND) & Elidable & MatchAddrMode(2) & MatchParameter(3) & Not(ReadsX)) ~
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(Linear & Not(ConcernsA) & Not(ConcernsX)).?.capture(11) ~
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(HasOpcode(STA) & Elidable & MatchAddrMode(4) & MatchParameter(5) & HasAddrModeIn(SaxModes) & DontMatchParameter(0)) ~
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(Linear & Not(ConcernsA) & Not(ConcernsX) & Not(ChangesMemory)).?.capture(12) ~
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(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ConcernsX)).*.capture(13) ~ OverwritesX ~~> { (code, ctx) =>
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(Linear & Not(ConcernsA) & Not(ConcernsX) & DoesntChangeMemoryAt(0, 1)).*.capture(11) ~
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(HasOpcode(STA) & Elidable & MatchAddrMode(4) & MatchParameter(5) & HasAddrModeIn(SaxModes) & DoesntChangeMemoryAt(0, 1)) ~
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(Linear & Not(ConcernsA) & Not(ConcernsX) & DoesntChangeMemoryAt(0, 1)).*.capture(12) ~
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(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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val lda = code.head
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val ldx = AssemblyLine(LDX, ctx.get[AddrMode.Value](2), ctx.get[Constant](3))
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val sax = AssemblyLine(SAX, ctx.get[AddrMode.Value](4), ctx.get[Constant](5))
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val fragment0 = lda :: ctx.get[List[AssemblyLine]](10)
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val fragment1 = ldx :: ctx.get[List[AssemblyLine]](11)
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val fragment2 = sax :: ctx.get[List[AssemblyLine]](12)
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val fragment3 = ctx.get[List[AssemblyLine]](13)
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List(fragment0, fragment1, fragment2, fragment3).flatten
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List(fragment0, fragment1, fragment2).flatten
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},
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)
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@ -104,10 +100,10 @@ object UndocumentedOptimizations {
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(Elidable & HasOpcode(LDA) & HasImmediate(0) & HasClear(State.C)) ~~> (_ => List(AssemblyLine.immediate(ANC, 0))),
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(Elidable & HasOpcode(AND) & MatchImmediate(0)) ~
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Where(c => andConstant(c.get[Constant](0), 0x80).contains(0)) ~
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(Elidable & HasOpcode(CLC)) ~~> ((_, ctx) => List(AssemblyLine.immediate(ANC, ctx.get[Int](0)))),
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(Elidable & HasOpcode(CLC)) ~~> ((_, ctx) => List(AssemblyLine.immediate(ANC, ctx.get[Constant](0)))),
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(Elidable & HasOpcode(AND) & MatchImmediate(0)) ~
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Where(c => andConstant(c.get[Constant](0), 0x80).contains(0x80)) ~
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(Elidable & HasOpcode(SEC)) ~~> ((_, ctx) => List(AssemblyLine.immediate(ANC, ctx.get[Int](0)))),
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(Elidable & HasOpcode(SEC)) ~~> ((_, ctx) => List(AssemblyLine.immediate(ANC, ctx.get[Constant](0)))),
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(Elidable & HasOpcode(AND) & MatchImmediate(0)) ~
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(Elidable & HasOpcode(CMP) & HasImmediate(0x80) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> ((_, ctx) => List(AssemblyLine.immediate(ANC, ctx.get[Int](0)))),
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(Elidable & HasOpcode(AND) & MatchImmediate(0)) ~
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@ -122,29 +118,29 @@ object UndocumentedOptimizations {
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val UseSbx = new RuleBasedAssemblyOptimization("Using undocumented instruction SBX",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(DEX) & DoesntMatterWhatItDoesWith(State.A, State.C)).+.captureLength(0) ~
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(Elidable & HasOpcode(DEX) & DoesntMatterWhatItDoesWith(State.A)).+.captureLength(0) ~
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Where(_.get[Int](0) > 2) ~~> ((_, ctx) => List(
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AssemblyLine.implied(TXA),
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AssemblyLine.immediate(SBX, ctx.get[Int](0)),
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AssemblyLine.immediate(SBX, ctx.get[Constant](0)),
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)),
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(Elidable & HasOpcode(INX) & DoesntMatterWhatItDoesWith(State.A, State.C)).+.captureLength(0) ~
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(Elidable & HasOpcode(INX) & DoesntMatterWhatItDoesWith(State.A)).+.captureLength(0) ~
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Where(_.get[Int](0) > 2) ~~> ((_, ctx) => List(
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AssemblyLine.implied(TXA),
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AssemblyLine.immediate(SBX, 256 - ctx.get[Int](0)),
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AssemblyLine.immediate(SBX, Constant.Zero - ctx.get[Constant](0)),
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)),
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HasOpcode(TXA) ~
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(Elidable & HasOpcode(CLC)).? ~
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(Elidable & HasClear(State.C) & HasClear(State.D) & HasOpcode(ADC) & MatchImmediate(0)) ~
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(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.C, State.A)) ~~> ((code, ctx) => List(
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code.head,
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AssemblyLine.immediate(SBX, 256 - ctx.get[Int](0)),
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AssemblyLine.immediate(SBX, Constant.Zero - ctx.get[Constant](0)),
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)),
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HasOpcode(TXA) ~
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(Elidable & HasOpcode(SEC)).? ~
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(Elidable & HasSet(State.C) & HasClear(State.D) & HasOpcode(SBC) & MatchImmediate(0)) ~
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(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.C, State.A)) ~~> ((code, ctx) => List(
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code.head,
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AssemblyLine.immediate(SBX, ctx.get[Int](0)),
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AssemblyLine.immediate(SBX, ctx.get[Constant](0)),
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)),
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)
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@ -152,11 +148,11 @@ object UndocumentedOptimizations {
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val UseAlr = new RuleBasedAssemblyOptimization("Using undocumented instruction ALR",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcode(AND) & HasAddrMode(Immediate)) ~
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(Elidable & HasOpcode(LSR) & HasAddrMode(Implied)) ~~> { (code, ctx) =>
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(Elidable & HasOpcode(LSR) & HasAddrMode(Implied)) ~~> { code =>
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List(AssemblyLine.immediate(ALR, code.head.parameter))
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},
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(Elidable & HasOpcode(LSR) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(CLC)) ~~> { (code, ctx) =>
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(Elidable & HasOpcode(CLC)) ~~> { _ =>
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List(AssemblyLine.immediate(ALR, 0xFE))
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},
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)
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@ -164,7 +160,7 @@ object UndocumentedOptimizations {
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val UseArr = new RuleBasedAssemblyOptimization("Using undocumented instruction ARR",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(HasClear(State.D) & Elidable & HasOpcode(AND) & HasAddrMode(Immediate)) ~
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(Elidable & HasOpcode(ROR) & HasAddrMode(Implied) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
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(Elidable & HasOpcode(ROR) & HasAddrMode(Implied) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { code =>
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List(AssemblyLine.immediate(ARR, code.head.parameter))
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},
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)
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@ -193,7 +189,7 @@ object UndocumentedOptimizations {
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}
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val UseSlo = new RuleBasedAssemblyOptimization("Using undocumented instruction SLO",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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trivialSequence1(ASL, ORA, Not(ConcernsC), SLO),
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trivialSequence2(ASL, ORA, Not(ConcernsC), SLO),
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trivialCommutativeSequence(ASL, ORA, SLO),
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@ -206,11 +202,16 @@ object UndocumentedOptimizations {
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(Linear & Not(ConcernsMemory) & Not(ChangesA)).*.capture(2) ~
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(Elidable & HasOpcode(ASL) & HasAddrMode(Implied)) ~
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(Linear & Not(ConcernsMemory) & Not(ChangesA) & Not(ReadsC) & Not(ReadsNOrZ)).*.capture(3) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (_, ctx) =>
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List(AssemblyLine.immediate(LDA, 0), AssemblyLine(SRE, ctx.get[AddrMode.Value](0), ctx.get[Constant](1))) ++
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ctx.get[List[AssemblyLine]](2) ++
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ctx.get[List[AssemblyLine]](3)
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},
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(Elidable & HasA(0) & HasOpcode(ASL) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & DoesntChangeMemoryAt(0, 1) & Not(ChangesA)).* ~
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(Elidable & HasA(0) & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.Z, State.N, State.C)) ~~> { code =>
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code.head.copy(opcode = SLO) :: code.tail.init
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},
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)
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val UseSre = new RuleBasedAssemblyOptimization("Using undocumented instruction SRE",
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@ -227,7 +228,7 @@ object UndocumentedOptimizations {
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(Linear & Not(ConcernsMemory) & Not(ChangesA)).*.capture(2) ~
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(Elidable & HasOpcode(LSR) & HasAddrMode(Implied)) ~
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(Linear & Not(ConcernsMemory) & Not(ChangesA) & Not(ReadsC) & Not(ReadsNOrZ)).*.capture(3) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (_, ctx) =>
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List(AssemblyLine.immediate(LDA, 0), AssemblyLine(SRE, ctx.get[AddrMode.Value](0), ctx.get[Constant](1))) ++
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ctx.get[List[AssemblyLine]](2) ++
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ctx.get[List[AssemblyLine]](3)
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@ -262,7 +263,11 @@ object UndocumentedOptimizations {
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(Elidable & HasOpcode(LDA) & Not(HasAddrMode(Immediate)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(CMP) & MatchAddrMode(2) & MatchParameter(3) & DoesntMatterWhatItDoesWith(State.V, State.C, State.N, State.A)) ~~> { code =>
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List(code(2).copy(opcode = LDA), code(1).copy(opcode = DCP))
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}
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},
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(Elidable & HasOpcode(DEC) & Not(HasAddrMode(Immediate)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(LDA) & Not(HasAddrMode(Immediate)) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.V, State.C, State.N, State.A)) ~~> { code =>
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List(AssemblyLine.immediate(LDA, 0), code(1).copy(opcode = DCP))
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},
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)
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val UseIsc = new RuleBasedAssemblyOptimization("Using undocumented instruction ISC",
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@ -9,23 +9,49 @@ import org.scalatest.{FunSuite, Matchers}
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class IllegalSuite extends FunSuite with Matchers {
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test("ALR test 1") {
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EmuUndocumentedRun("""
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| byte input @$cfff
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| void main () {
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| init()
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| output = (input & 0x45) >> 1
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| }
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| void init() {
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| input = $45
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| }
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""".stripMargin)
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m.readByte(0xc000) should equal(0x22)
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}
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test("ALR test 2") {
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EmuUndocumentedRun("""
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| byte input @$cfff
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| void main () {
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| output = (input & 0x45) >> 1
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| init()
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| output = (input >> 1) + 1
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| }
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| void init() {
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| input = $8A
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| }
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""".stripMargin)
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m.readByte(0xc000) should equal(0x46)
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}
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test("ANC test") {
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| byte input @$cfff
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| void main () {
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| init()
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| output = (input & $45) + 1
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| }
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| void init() {
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| input = $45
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| }
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""".stripMargin)
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m.readByte(0xc000) should equal(0x46)
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}
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test("ISC/DCP test") {
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@ -48,4 +74,114 @@ class IllegalSuite extends FunSuite with Matchers {
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m.readByte(0xc005) should equal(37)
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m.readByte(0xc007) should equal(51)
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}
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test("DCP test") {
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| array integers [10] @$c060
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| void main () {
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| byte i
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| for i,0,paralleluntil,10 { integers[i] += i }
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| output = loop()
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| }
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| byte loop () {
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| byte result
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| result = 0
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| byte i
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| i = 7
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| do {
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| result += integers[i]
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| integers[i + i] += 1
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| integers[i] += 1
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| i -= 1
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| } while i != 0
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| return result
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| }
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""".stripMargin)
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m.readByte(0xc000) should equal(28)
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}
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test("SLO test") {
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val m = EmuUndocumentedRun("""
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| long output @$c000
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| byte main () {
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| output = five()
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| output <<= 1
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| return output
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| }
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| byte five () {
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| return 5
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| }
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""".stripMargin)
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m.readLong(0xc000) should equal(10)
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}
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test("SAX test") {
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| void main () {
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| byte a
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| byte b
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| byte c
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| b = five(a)
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| c = five(a)
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| a = c
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| five(a)
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| c = a & b
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| output = a + b + c
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| }
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| byte five (byte ignored) {
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| return 5
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| }
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""".stripMargin)
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m.readLong(0xc000) should equal(15)
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}
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test("LAX test 1") {
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val m = EmuUndocumentedRun("""
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| word output @$c000
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| void main () {
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| output = five(5)
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| }
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| word five (byte a) {
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| return a:a
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| }
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""".stripMargin)
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m.readLong(0xc000) should equal(0x505)
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}
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test("LAX test 2") {
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val m = EmuUndocumentedRun("""
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| byte output @$c000
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| void main () {
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| output = five(1)
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| }
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| byte five (byte a) {
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| byte b
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| b = a
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| a += 4
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| return b & a
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| }
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""".stripMargin)
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m.readLong(0xc000) should equal(1)
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}
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test("SBX test 1") {
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val m = EmuUndocumentedRun("""
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| array output [10] @$c000
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| void main () {
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| output[6] = 7
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| five(1)
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| }
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| void five (byte a) {
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| byte b
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| b = a
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| output[b] += 1
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| b += 5
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| output[b] += 1
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| }
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""".stripMargin)
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m.readByte(0xc006) should equal(8)
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}
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}
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