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Z80: optimization improvements

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This commit is contained in:
Karol Stasiak 2021-02-26 23:12:43 +01:00
parent 84d707b932
commit 83393d49f1
3 changed files with 22 additions and 0 deletions
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9
src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
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@ -371,6 +371,15 @@ object AlwaysGoodI80Optimizations {
(Linear & Not(ConcernsMemory)).* ~
(HasOpcode(LD_16) & HasTargetRegister(MEM_ABS_16) & MatchParameter(0)) ~~> (_.tail),
// 72-77
for6Registers(reg => {
(Elidable & HasOpcode(LD) & Is8BitLoad(A, reg)) ~
(Elidable & HasOpcodeIn(Set(INC, DEC)) & HasRegisterParam(A)) ~
(Elidable & HasOpcode(LD) & Is8BitLoad(reg, A)) ~~> { code =>
List(code(1).copy(registers = OneRegister(reg)), code.head)
}
}),
)
val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",

12
src/main/scala/millfork/assembly/z80/opt/AlwaysGoodZ80Optimizations.scala
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@ -110,6 +110,18 @@ object AlwaysGoodZ80Optimizations {
List(
code.head.copy(registers = TwoRegisters(ZRegister.BC, ZRegister.MEM_ABS_16))
)),
(Elidable & Is16BitLoad(ZRegister.HL, ZRegister.MEM_ABS_16)) ~
(Elidable & Is8BitLoad(ZRegister.E, ZRegister.L)) ~
(Elidable & Is8BitLoad(ZRegister.D, ZRegister.H) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> (code =>
List(
code.head.copy(registers = TwoRegisters(ZRegister.DE, ZRegister.MEM_ABS_16))
)),
(Elidable & Is16BitLoad(ZRegister.HL, ZRegister.MEM_ABS_16)) ~
(Elidable & Is8BitLoad(ZRegister.C, ZRegister.L)) ~
(Elidable & Is8BitLoad(ZRegister.B, ZRegister.H) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> (code =>
List(
code.head.copy(registers = TwoRegisters(ZRegister.BC, ZRegister.MEM_ABS_16))
)),
(Elidable & Is16BitLoad(ZRegister.HL, ZRegister.MEM_ABS_16)) ~
(Elidable & HasOpcode(EX_DE_HL) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> (code =>
List(

1
src/main/scala/millfork/assembly/z80/opt/ByteVariableToRegisterOptimization.scala
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@ -210,6 +210,7 @@ object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
}
var bonus = CyclesAndBytes.Zero
if (vs.variablesWithRegisterHint(v.name)) bonus += CyclesAndBytes(16, 16)
if (vs.paramVariables(v.name)) bonus += (if (register == ZRegister.A) CyclesAndBytes(-13, -3) else CyclesAndBytes(-17, -4))
if (id.startsWith("IX+") || id.startsWith("IY+")) bonus += savingsForRemovingOneStackVariable
if (id.startsWith("SP+") || v.isVolatile) None
else canBeInlined(id, synced = false, register, Some(false), Some(false), Some(false), vs.codeWithFlow.slice(range.start, range.end)).map { score =>