diff --git a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
index 9156bccc..7e184c22 100644
--- a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
+++ b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
@@ -1699,6 +1699,11 @@ object AlwaysGoodOptimizations {
       (Elidable & HasOpcodeIn(ROL, ROR) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { code =>
       code.last.copy(addrMode = AddrMode.Implied, parameter = Constant.Zero) :: code.init
     },
+    (Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~
+      (Linear & DoesNotConcernMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0) & Not(ConcernsA)).* ~
+      (Elidable & HasOpcodeIn(ROL, ROR, LSR, ASL) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.A)) ~~> { code =>
+      code.tail.init ++ List(code.last.copy(addrMode = AddrMode.Implied, parameter = Constant.Zero), code.head)
+    },
   )
 
   val SmarterShiftingBytes = new RuleBasedAssemblyOptimization("Smarter shifting of bytes",
diff --git a/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala b/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
index 1f86216b..ce91025d 100644
--- a/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
+++ b/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
@@ -5,6 +5,7 @@ import millfork.assembly.z80._
 import millfork.node.ZRegister
 import ZOpcode._
 import ZRegister._
+import millfork.env.Constant
 
 
 /**
@@ -46,6 +47,33 @@ object LaterI80Optimizations {
       (Elidable & HasOpcode(DEC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
       (HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.implied(CCF), ZLine.imm8(SBC, 0), code.last)),
 
+    (Elidable & Is8BitLoadTo(B) & Match8BitImmediate(1)) ~
+      (Elidable & Is8BitLoadTo(C) & Match8BitImmediate(0)) ~~> { (code, ctx) =>
+      val l = ctx.get[Constant](0)
+      val h = ctx.get[Constant](1)
+      List(ZLine.ldImm16(BC, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
+    },
+
+    (Elidable & Is8BitLoadTo(C) & Match8BitImmediate(0)) ~
+      (Elidable & Is8BitLoadTo(B) & Match8BitImmediate(1)) ~~> { (code, ctx) =>
+      val l = ctx.get[Constant](0)
+      val h = ctx.get[Constant](1)
+      List(ZLine.ldImm16(BC, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
+    },
+
+    (Elidable & Is8BitLoadTo(D) & Match8BitImmediate(1)) ~
+      (Elidable & Is8BitLoadTo(E) & Match8BitImmediate(0)) ~~> { (code, ctx) =>
+      val l = ctx.get[Constant](0)
+      val h = ctx.get[Constant](1)
+      List(ZLine.ldImm16(DE, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
+    },
+
+    (Elidable & Is8BitLoadTo(E) & Match8BitImmediate(0)) ~
+      (Elidable & Is8BitLoadTo(D) & Match8BitImmediate(1)) ~~> { (code, ctx) =>
+      val l = ctx.get[Constant](0)
+      val h = ctx.get[Constant](1)
+      List(ZLine.ldImm16(DE, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
+    },
   )
 
   val FreeHL = new RuleBasedAssemblyOptimization("Free HL (later)",
diff --git a/src/main/scala/millfork/assembly/z80/opt/LaterIntel8080Optimizations.scala b/src/main/scala/millfork/assembly/z80/opt/LaterIntel8080Optimizations.scala
index 998a17f7..f6e9b381 100644
--- a/src/main/scala/millfork/assembly/z80/opt/LaterIntel8080Optimizations.scala
+++ b/src/main/scala/millfork/assembly/z80/opt/LaterIntel8080Optimizations.scala
@@ -5,6 +5,7 @@ import millfork.assembly.z80.{ZLine, ZOpcode}
 import millfork.node.ZRegister
 import ZOpcode._
 import ZRegister._
+import millfork.env.Constant
 
 /**
   * @author Karol Stasiak
@@ -24,8 +25,22 @@ object LaterIntel8080Optimizations {
     },
   )
 
+  val Store16BitConstantsDirectly = new RuleBasedAssemblyOptimization("Store 16-bit constants directly ",
+    needsFlowInfo = FlowInfoRequirement.BothFlows,
+
+      (Elidable & Is8BitLoad(MEM_ABS_8, A) & MatchParameter(1) & MatchRegister(A, 0)) ~
+      (Elidable & Is8BitLoad(MEM_ABS_8, A) & MatchParameter(2) & DoesntMatterWhatItDoesWith(A) & DoesntMatterWhatItDoesWithFlags & DoesntMatterWhatItDoesWith(HL)) ~
+      Where(ctx => ctx.get[Constant](1).+(1).quickSimplify == ctx.get[Constant](2)) ~~> { (code, ctx) =>
+      val l = ctx.get[Int](0)
+      val addr = ctx.get[Constant](1)
+      List(
+        ZLine.ldImm16(HL, 0x101 * l).pos(code.head.source),
+        ZLine.ldAbs16(addr, HL).pos(code.tail.map(_.source)))
+    },
+  )
+
   val All: List[AssemblyOptimization[ZLine]] = List(
-    UseExDeHl
+    UseExDeHl, Store16BitConstantsDirectly
   )
 
 }