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Few more minor optimizations
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@ -1699,6 +1699,11 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcodeIn(ROL, ROR) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { code =>
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code.last.copy(addrMode = AddrMode.Implied, parameter = Constant.Zero) :: code.init
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},
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & DoesNotConcernMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0) & Not(ConcernsA)).* ~
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(Elidable & HasOpcodeIn(ROL, ROR, LSR, ASL) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.A)) ~~> { code =>
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code.tail.init ++ List(code.last.copy(addrMode = AddrMode.Implied, parameter = Constant.Zero), code.head)
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},
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)
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val SmarterShiftingBytes = new RuleBasedAssemblyOptimization("Smarter shifting of bytes",
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@ -5,6 +5,7 @@ import millfork.assembly.z80._
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import millfork.node.ZRegister
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import ZOpcode._
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import ZRegister._
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import millfork.env.Constant
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/**
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@ -46,6 +47,33 @@ object LaterI80Optimizations {
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(Elidable & HasOpcode(DEC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
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(HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.implied(CCF), ZLine.imm8(SBC, 0), code.last)),
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(Elidable & Is8BitLoadTo(B) & Match8BitImmediate(1)) ~
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(Elidable & Is8BitLoadTo(C) & Match8BitImmediate(0)) ~~> { (code, ctx) =>
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val l = ctx.get[Constant](0)
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val h = ctx.get[Constant](1)
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List(ZLine.ldImm16(BC, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
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},
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(Elidable & Is8BitLoadTo(C) & Match8BitImmediate(0)) ~
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(Elidable & Is8BitLoadTo(B) & Match8BitImmediate(1)) ~~> { (code, ctx) =>
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val l = ctx.get[Constant](0)
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val h = ctx.get[Constant](1)
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List(ZLine.ldImm16(BC, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
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},
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(Elidable & Is8BitLoadTo(D) & Match8BitImmediate(1)) ~
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(Elidable & Is8BitLoadTo(E) & Match8BitImmediate(0)) ~~> { (code, ctx) =>
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val l = ctx.get[Constant](0)
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val h = ctx.get[Constant](1)
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List(ZLine.ldImm16(DE, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
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},
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(Elidable & Is8BitLoadTo(E) & Match8BitImmediate(0)) ~
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(Elidable & Is8BitLoadTo(D) & Match8BitImmediate(1)) ~~> { (code, ctx) =>
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val l = ctx.get[Constant](0)
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val h = ctx.get[Constant](1)
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List(ZLine.ldImm16(DE, h.asl(8).+(l).quickSimplify).pos(code.map(_.source)))
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},
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)
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val FreeHL = new RuleBasedAssemblyOptimization("Free HL (later)",
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@ -5,6 +5,7 @@ import millfork.assembly.z80.{ZLine, ZOpcode}
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import millfork.node.ZRegister
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import ZOpcode._
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import ZRegister._
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import millfork.env.Constant
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/**
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* @author Karol Stasiak
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@ -24,8 +25,22 @@ object LaterIntel8080Optimizations {
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},
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)
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val Store16BitConstantsDirectly = new RuleBasedAssemblyOptimization("Store 16-bit constants directly ",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & Is8BitLoad(MEM_ABS_8, A) & MatchParameter(1) & MatchRegister(A, 0)) ~
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(Elidable & Is8BitLoad(MEM_ABS_8, A) & MatchParameter(2) & DoesntMatterWhatItDoesWith(A) & DoesntMatterWhatItDoesWithFlags & DoesntMatterWhatItDoesWith(HL)) ~
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Where(ctx => ctx.get[Constant](1).+(1).quickSimplify == ctx.get[Constant](2)) ~~> { (code, ctx) =>
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val l = ctx.get[Int](0)
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val addr = ctx.get[Constant](1)
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List(
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ZLine.ldImm16(HL, 0x101 * l).pos(code.head.source),
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ZLine.ldAbs16(addr, HL).pos(code.tail.map(_.source)))
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},
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)
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val All: List[AssemblyOptimization[ZLine]] = List(
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UseExDeHl
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UseExDeHl, Store16BitConstantsDirectly
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)
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}
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