From a16f66203181b11cb2d3530662e5df81bd0aab3f Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Sun, 10 Jun 2018 23:44:45 +0200 Subject: [PATCH] Optimization fixes --- src/main/scala/millfork/assembly/opt/LaterOptimizations.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/millfork/assembly/opt/LaterOptimizations.scala b/src/main/scala/millfork/assembly/opt/LaterOptimizations.scala index 78b97c37..e545a18d 100644 --- a/src/main/scala/millfork/assembly/opt/LaterOptimizations.scala +++ b/src/main/scala/millfork/assembly/opt/LaterOptimizations.scala @@ -118,7 +118,7 @@ object LaterOptimizations { private def TwoIdenticalLoadsWithNoFlagChangeInBetween(opcode: Opcode.Value, middle: AssemblyLinePattern) = { (HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~ - (LinearOrLabel & Not(ChangesMemory) & middle & Not(ChangesNAndZ)).* ~ + (LinearOrLabel & Not(ChangesMemory) & DoesntChangeIndexingInAddrMode(0) & middle & Not(ChangesNAndZ)).* ~ (HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { c => c.init } @@ -134,7 +134,7 @@ object LaterOptimizations { private def TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(opcode: Opcode.Value, middle: AssemblyLinePattern) = { ((HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~ - (LinearOrLabel & Not(ChangesMemory) & middle).*).capture(2) ~ + (LinearOrLabel & Not(ChangesMemory) & DoesntChangeIndexingInAddrMode(0) & middle).*).capture(2) ~ (HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~ ((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) => ctx.get[List[AssemblyLine]](2) ++ ctx.get[List[AssemblyLine]](3)