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6502: Fix optimizations involving the zeropage pseudoregister

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Karol Stasiak 2019-07-23 23:16:37 +02:00
parent 45c137e2c0
commit a25f6ca3f6
3 changed files with 8 additions and 6 deletions
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2
CHANGELOG.md
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@ -16,6 +16,8 @@
* 6502: Fixed expressions of form `p[i] <<= 1`.
* 6502: Fixed optimizations involving the zeropage pseudoregister.
* Other fixes and improvements.
## 0.3.4

10
src/main/scala/millfork/assembly/mos/opt/CoarseFlowAnalyzer.scala
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@ -86,24 +86,24 @@ object CoarseFlowAnalyzer {
case AssemblyLine0(op, Immediate | WordImmediate, NumericConstant(nn, _)) if FlowAnalyzerForImmediate.hasDefinition(op) =>
currentStatus = FlowAnalyzerForImmediate.get(op)(nn.toInt, currentStatus)
case AssemblyLine0(STA, _, MemoryAddressConstant(th: Thing))
case AssemblyLine0(STA, ZeroPage | Absolute | LongAbsolute, MemoryAddressConstant(th: Thing))
if th.name == "__sp" =>
currentStatus = FlowAnalyzerForTheRest.get(STA)(currentStatus, None, true)
staSpIsNow = true
case AssemblyLine0(op, _, MemoryAddressConstant(th: Thing))
case AssemblyLine0(op, ZeroPage | Absolute | LongAbsolute, MemoryAddressConstant(th: Thing))
if th.name == "__sp" && FlowAnalyzerForTheRest.hasDefinition(op) =>
currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus, None, true)
case AssemblyLine0(op, _, MemoryAddressConstant(th: Thing))
case AssemblyLine0(op, ZeroPage | Absolute | LongAbsolute, MemoryAddressConstant(th: Thing))
if th.name == "__reg" && FlowAnalyzerForTheRest.hasDefinition(op) =>
currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus, Some(0), false)
case AssemblyLine0(op, _, CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th: Thing), NumericConstant(n, _)))
case AssemblyLine0(op, ZeroPage | Absolute | LongAbsolute, CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th: Thing), NumericConstant(n, _)))
if th.name == "__reg" && FlowAnalyzerForTheRest.hasDefinition(op) =>
currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus, Some(n.toInt), false)
case AssemblyLine0(op, _, _) if FlowAnalyzerForTheRest.hasDefinition(op) =>
case AssemblyLine0(op, ZeroPage | Absolute | LongAbsolute | Relative | LongRelative, _) if FlowAnalyzerForTheRest.hasDefinition(op) =>
currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus, None, false)
case AssemblyLine0(opcode, addrMode, _) =>

2
src/main/scala/millfork/assembly/mos/opt/ZeropageRegisterOptimizations.scala
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@ -389,7 +389,7 @@ object ZeropageRegisterOptimizations {
val LoadingKnownValue = new RuleBasedAssemblyOptimization("Loading known value from register",
needsFlowInfo = FlowInfoRequirement.ForwardFlow,
MultipleAssemblyRules((0 to 4).map{ zregIndex =>
(Elidable & HasOpcodeIn(LDA, ADC, SBC, CMP, EOR, AND, ORA, LDX, LDY, CPX, CPY) & RefersToOrUses("__reg", zregIndex) & MatchZpReg(1, zregIndex)) ~~> { (code, ctx) =>
(Elidable & HasOpcodeIn(LDA, ADC, SBC, CMP, EOR, AND, ORA, LDX, LDY, CPX, CPY) & RefersTo("__reg", zregIndex) & MatchZpReg(1, zregIndex)) ~~> { (code, ctx) =>
List(AssemblyLine.immediate(code.head.opcode, ctx.get[Int](1)))
}
})