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Lazy flow analysis
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@ -8,7 +8,16 @@ import millfork.env.{Label, MemoryAddressConstant, NormalFunction}
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* @author Karol Stasiak
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*/
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case class FlowInfo(statusBefore: CpuStatus, importanceAfter: CpuImportance, labelUseCountMap: Option[Map[String, Int]]) {
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class FlowHolder(_statusBefore: () => List[CpuStatus], _importanceAfter: () => List[CpuImportance]) {
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lazy val statusBefore: List[CpuStatus] = _statusBefore()
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lazy val importanceAfter: List[CpuImportance] = _importanceAfter()
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}
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case class FlowInfo(holder: FlowHolder, index: Int, _labelUseCountMap: () => Option[Map[String, Int]]) {
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lazy val statusBefore: CpuStatus = holder.statusBefore(index)
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lazy val importanceAfter = holder.importanceAfter(index)
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lazy val labelUseCountMap: Option[Map[String, Int]] = _labelUseCountMap()
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def hasClear(state: State.Value): Boolean = statusBefore.hasClear(state)
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@ -19,35 +28,36 @@ case class FlowInfo(statusBefore: CpuStatus, importanceAfter: CpuImportance, lab
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def labelUseCount(label: String): Int = labelUseCountMap.map(_.getOrElse(label, 0)).getOrElse(-1)
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}
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object FlowInfo {
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val Default = FlowInfo(CpuStatus(), CpuImportance(), None)
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}
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object FlowAnalyzer {
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private val EmptyCpuStatus = CpuStatus()
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private val EmptyCpuImportance = CpuImportance()
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def analyze(f: NormalFunction, code: List[AssemblyLine], options: CompilationOptions, req: FlowInfoRequirement.Value): List[(FlowInfo, AssemblyLine)] = {
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val forwardFlow = req match {
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case FlowInfoRequirement.BothFlows | FlowInfoRequirement.ForwardFlow =>
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if (options.flag(CompilationFlag.DetailedFlowAnalysis)) {
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QuantumFlowAnalyzer.analyze(f, code).map(_.collapse)
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() => QuantumFlowAnalyzer.analyze(f, code).map(_.collapse)
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} else {
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CoarseFlowAnalyzer.analyze(f, code)
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() => CoarseFlowAnalyzer.analyze(f, code)
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}
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case FlowInfoRequirement.BackwardFlow | FlowInfoRequirement.JustLabels | FlowInfoRequirement.NoRequirement =>
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List.fill(code.size)(CpuStatus())
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() => List.fill(code.size)(EmptyCpuStatus)
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}
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val reverseFlow = req match {
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case FlowInfoRequirement.BothFlows | FlowInfoRequirement.BackwardFlow =>
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ReverseFlowAnalyzer.analyze(f, code)
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() => ReverseFlowAnalyzer.analyze(f, code)
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case FlowInfoRequirement.ForwardFlow | FlowInfoRequirement.JustLabels | FlowInfoRequirement.NoRequirement =>
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List.fill(code.size)(CpuImportance())
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() => List.fill(code.size)(EmptyCpuImportance)
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}
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val labelMap = req match {
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val labelMap: (() => Option[Map[String, Int]]) = () => req match {
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case FlowInfoRequirement.NoRequirement => None
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case _ => Some(code.flatMap {
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case AssemblyLine(op, _, MemoryAddressConstant(Label(l)), _) if op != Opcode.LABEL => Some(l)
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case _ => None
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}.groupBy(identity).mapValues(_.size))
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}
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forwardFlow.zip(reverseFlow).map { case (s, i) => FlowInfo(s, i, labelMap) }.zip(code)
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val holder = new FlowHolder(forwardFlow, reverseFlow)
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code.zipWithIndex.map{ case (line, i) => FlowInfo(holder, i, labelMap) -> line}
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}
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}
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