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6502: Improve memset
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parent
46ce602a3e
commit
b01c440cf0
@ -1,8 +1,9 @@
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package millfork.compiler.mos
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import millfork.CompilationFlag
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import millfork.assembly.mos.AssemblyLine
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import millfork.compiler.{BranchSpec, CompilationContext}
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import millfork.env.{Label, NumericConstant, Type, VariableInMemory}
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import millfork.env.{NumericConstant, Type, VariableInMemory}
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import millfork.node._
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import millfork.assembly.mos.Opcode._
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@ -32,43 +33,93 @@ object MosBulkMemoryOperations {
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case Some(c) => c.quickSimplify
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case _ => return MosStatementCompiler.compileForStatement(ctx, f)
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}
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val loadReg = MosExpressionCompiler.compile(ctx, SumExpression(List(false -> f.start, false -> target.index), decimal = false), Some(w -> reg), BranchSpec.None)
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val useTwoRegs = ctx.options.flag(CompilationFlag.OptimizeForSpeed) && ctx.options.zpRegisterSize >= 4
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val loadReg = MosExpressionCompiler.compile(ctx, SumExpression(List(false -> f.start, false -> target.index), decimal = false), Some(w -> reg), BranchSpec.None) ++ (
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if (useTwoRegs) List(AssemblyLine.zeropage(LDA, reg), AssemblyLine.zeropage(STA, reg,2), AssemblyLine.zeropage(LDA, reg,1), AssemblyLine.zeropage(STA, reg,3))
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else Nil
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)
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val loadSource = MosExpressionCompiler.compileToA(ctx, source)
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val loadAll = if (MosExpressionCompiler.changesZpreg(loadSource, 0) || MosExpressionCompiler.changesZpreg(loadSource, 1)) {
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loadSource ++ MosExpressionCompiler.preserveRegisterIfNeeded(ctx, MosRegister.A, loadReg)
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} else {
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loadReg ++ loadSource
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}
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val wholePageCount = size.hiByte
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val setWholePages = wholePageCount match {
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case NumericConstant(0, _) => Nil
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case NumericConstant(1, _) =>
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val label = ctx.nextLabel("ms")
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List(
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val wholePageCount = size.hiByte.quickSimplify
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def fillOnePage: List[AssemblyLine] = {
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val label = ctx.nextLabel("ms")
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if (useTwoRegs) {
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if (ctx.options.flag(CompilationFlag.OptimizeForSonicSpeed)) {
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List(
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AssemblyLine.immediate(LDY, 0x80),
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AssemblyLine.label(label),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.indexedY(STA, reg, 2),
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AssemblyLine.implied(INY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.indexedY(STA, reg, 2),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, label))
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} else if (ctx.options.flag(CompilationFlag.OptimizeForSpeed)) {
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List(
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AssemblyLine.immediate(LDY, 0x80),
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AssemblyLine.label(label),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.indexedY(STA, reg, 2),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, label))
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} else ???
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} else {
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if (ctx.options.flag(CompilationFlag.OptimizeForSonicSpeed)) {
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List(
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AssemblyLine.immediate(LDY, 0),
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AssemblyLine.label(label),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, label))
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} else if (ctx.options.flag(CompilationFlag.OptimizeForSpeed)) {
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List(
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AssemblyLine.immediate(LDY, 0),
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AssemblyLine.label(label),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, label))
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} else {
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List(
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AssemblyLine.immediate(LDY, 0),
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AssemblyLine.label(label),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, label))
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}
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}
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}
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val setWholePages = wholePageCount match {
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case NumericConstant(0, _) => Nil
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case NumericConstant(1, _) =>
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fillOnePage
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case _ =>
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val labelX = ctx.nextLabel("ms")
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val labelXSkip = ctx.nextLabel("ms")
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val labelY = ctx.nextLabel("ms")
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List(
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AssemblyLine.immediate(LDX, wholePageCount),
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AssemblyLine.relative(BEQ, labelXSkip),
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AssemblyLine.label(labelX),
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AssemblyLine.immediate(LDY, 0),
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AssemblyLine.label(labelY),
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AssemblyLine.indexedY(STA, reg),
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AssemblyLine.implied(INY),
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AssemblyLine.relative(BNE, labelY),
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AssemblyLine.label(labelX)) ++ fillOnePage ++ List(
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AssemblyLine.zeropage(INC, reg, 1),
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AssemblyLine.implied(DEX),
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AssemblyLine.relative(BNE, labelX),
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AssemblyLine.label(labelXSkip))
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}
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val restSize = size.loByte
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val restSize = size.loByte.quickSimplify
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val setRest = restSize match {
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case NumericConstant(0, _) => Nil
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case NumericConstant(1, _) =>
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