1
0
mirror of https://github.com/KarolS/millfork.git synced 2024-11-01 05:05:32 +00:00

6809: various assembly fixes

This commit is contained in:
Karol Stasiak 2020-06-09 21:43:04 +02:00
parent 7ba01f83e3
commit b0577270d5
3 changed files with 7 additions and 5 deletions

View File

@ -2318,6 +2318,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
def nameCheck(node: Node): Unit = node match {
case _:MosAssemblyStatement => ()
case _:Z80AssemblyStatement => ()
case _:M6809AssemblyStatement => ()
case _:DeclarationStatement => ()
case s:ForStatement =>
checkName[Variable]("Variable", s.variable, s.position)

View File

@ -153,12 +153,12 @@ class M6809Assembler(program: Program,
writeByte(bank, index, M6809Assembler.indexable(op) + 0x20)
val ri = getRegByte(register, indirect)
param match {
case NumericConstant(n, _) if !indirect && n >= -16 && n <= 15 =>
writeByte(bank, index + 1, ri + n.toInt.&(0x1f))
index + 2
case NumericConstant(0, _) =>
writeByte(bank, index + 1, 0x84 + ri)
index + 2
case NumericConstant(n, _) if !indirect && n >= -16 && n <= 15 =>
writeByte(bank, index + 1, ri + n.toInt.&(0x1f))
index + 2
case NumericConstant(n, _) if n >= -128 && n <= 127 =>
writeByte(bank, index + 1, 0x88 + ri)
writeWord(bank, index + 2, param)
@ -298,7 +298,7 @@ object M6809Assembler {
inab(CLR, 0x4f)
inab(COM, 0x43)
inab(DEC, 0x4a)
inab(INC, 0x48)
inab(INC, 0x4c)
inab(LSR, 0x44)
inab(NEG, 0x40)
inab(ROL, 0x49)

View File

@ -126,7 +126,7 @@ case class M6809Parser(filename: String,
} yield {
val effAddrMode = (addrModeOverride, addrMode) match {
case (Some(InherentA), Inherent) => InherentA
case (Some(InherentB), Inherent) => InherentA
case (Some(InherentB), Inherent) => InherentB
case (Some(InherentA | InherentB), _) =>
log.error("Inherent accumulator instructions cannot have parameters", Some(position))
addrMode
@ -171,6 +171,7 @@ case class M6809Parser(filename: String,
case M6809AssemblyStatement(MOpcode.RTI, _, _, _) => () // OK
case M6809AssemblyStatement(MOpcode.JMP, _, _, _) => () // OK
case M6809AssemblyStatement(MOpcode.BRA, _, _, _) => () // OK
case M6809AssemblyStatement(MOpcode.PULS, set:RegisterSet, _, _) if set.contains(M6809Register.PC) => () // OK
case _ =>
val validReturn = if (flags("interrupt")) "RTI" else "RTS"
log.warn(s"Non-macro assembly function `$name` should end in " + validReturn, Some(p))