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6502: Do not optimize away register restoration in interrupt routines (fixes #19)

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This commit is contained in:
Karol Stasiak 2019-11-13 19:04:37 +01:00
parent e2b7b28b63
commit b10d8d7eeb
2 changed files with 9 additions and 8 deletions
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5
src/main/scala/millfork/assembly/mos/opt/ReverseFlowAnalyzerPerImpliedOpcode.scala
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@ -44,8 +44,9 @@ object ReverseFlowAnalyzerPerImpiedOpcode {
RTL -> (_ => finalImportance),
RTI -> (_ => CpuImportance(
a = Unimportant, ah = Unimportant,
x = Unimportant, y = Unimportant, iz = Unimportant,
a = Important, ah = Important,
x = Important, y = Important, iz = Important,
r0 = Important, r1 = Important, r2 = Important, r3 = Important,
z = Unimportant, n = Unimportant, c = Unimportant, v = Unimportant, d = Unimportant,
m = Unimportant, w = Unimportant)),

12
src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala
View File

@ -51,13 +51,13 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
(if (ctx.options.flag(CompilationFlag.SoftwareStack)) {
List(
AssemblyLine.implied(PLA),
AssemblyLine.absolute(STA, ctx.env.get[ThingInMemory]("__sp")))
AssemblyLine.absolute(STA, ctx.env.get[ThingInMemory]("__sp")).copy(elidability = Elidability.Volatile))
} else Nil) ++ (if (zpRegisterSize > 0) {
val reg = env.get[VariableInMemory]("__reg")
(zpRegisterSize.-(1) to 0 by (-1)).flatMap { i =>
List(
AssemblyLine.implied(PLA),
AssemblyLine.zeropage(STA, reg,i))
AssemblyLine.zeropage(STA, reg,i).copy(elidability = Elidability.Volatile))
}.toList
} else Nil)
val someRegisterA = Some(b, RegisterVariable(MosRegister.A, b))
@ -70,7 +70,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
val lastByte = if (zpRegisterSize % 2 != 0) {
List(
AssemblyLine.implied(PLA),
AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1),
AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1).copy(elidability = Elidability.Volatile),
AssemblyLine.immediate(REP, 0x30))
} else {
List(AssemblyLine.immediate(REP, 0x30))
@ -78,7 +78,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
val remainingBytes = (zpRegisterSize.&(0xfe).-(2) to 0 by (-2)).flatMap { i =>
List(
AssemblyLine.implied(PLA_W),
AssemblyLine.zeropage(STA_W, reg, i))
AssemblyLine.zeropage(STA_W, reg, i).copy(elidability = Elidability.Volatile))
}
lastByte ++ remainingBytes ++
List(
@ -123,9 +123,9 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
} else {
plReg ++ List(
AssemblyLine.implied(PLA),
AssemblyLine.implied(TAY),
AssemblyLine.implied(TAY).copy(elidability = Elidability.Fixed),
AssemblyLine.implied(PLA),
AssemblyLine.implied(TAX),
AssemblyLine.implied(TAX).copy(elidability = Elidability.Fixed),
AssemblyLine.implied(PLA),
AssemblyLine.implied(RTI))
}