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Add memory barriers
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@ -2,6 +2,8 @@
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## Current version
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* Added `memory_barrier` macro.
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* Added `random` module.
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* Added `ensure_mixedcase` function and `oldpet` and `origpet` text encodings.
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@ -61,3 +61,11 @@ Various colour constants.
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Available for: VIC-20, C64, C264 series, ZX Spectrum.
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#### `macro void memory_barrier()`
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Informs the optimizer that at this point arbitrary memory has been accessed and either read or written by an external device.
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The optimizer should not optimize any memory accesses across that macro.
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Available for: all targets.
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@ -142,6 +142,7 @@ object OpcodeClasses {
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SLO, RLA, SRE, RRA,
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AHX, SHY, SHX, TAS, LAS,
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COP,
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CHANGED_MEM,
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)
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val ChangesMemoryIfNotImplied = Set(
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DEC, INC, ASL, ROL, LSR, ROR,
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@ -158,6 +159,7 @@ object OpcodeClasses {
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LAS,
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TRB, TSB,
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TRB_W, TSB_W,
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CHANGED_MEM,
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)
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val AccessesWordInMemory = Set(
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@ -332,7 +334,7 @@ object OpcodeClasses {
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CSH, CSL,
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TXY, TYX, XBA,
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PHD, PHB, PHK,
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DISCARD_AF, DISCARD_XF, DISCARD_YF)
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DISCARD_AF, DISCARD_XF, DISCARD_YF, CHANGED_MEM)
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val NoopDiscardsFlags = Set(DISCARD_AF, DISCARD_XF, DISCARD_YF)
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val DiscardsV = NoopDiscardsFlags | OverwritesV
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@ -120,7 +120,7 @@ object Opcode extends Enumeration {
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PHA_W, PLA_W,
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PHX_W, PHY_W, PLY_W, PLX_W,
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DISCARD_AF, DISCARD_XF, DISCARD_YF,
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DISCARD_AF, DISCARD_XF, DISCARD_YF, CHANGED_MEM,
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BYTE, LABEL = Value
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def widen(opcode: Opcode.Value): Option[Opcode.Value] = opcode match {
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@ -268,6 +268,7 @@ object HelperCheckers {
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val a2 = l2.addrMode
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if (goodAddrModes(a1) || goodAddrModes(a2)) return true
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if (badAddrModes(a1) || badAddrModes(a2)) return false
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if (l1.opcode == Opcode.CHANGED_MEM || l2.opcode == Opcode.CHANGED_MEM) return false
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if ((a1 == IndexedSY) != (a2 == IndexedSY)) return true // bold assertion, but usually true
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val p1 = l1.parameter
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val p2 = l2.parameter
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@ -868,6 +868,7 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
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import ZOpcode._
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import ZRegister._
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opcode match {
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case CHANGED_MEM => true
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case POP => true
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case LD | LD_16 | ADC_16 | ADD_16 | SBC_16 => registers match {
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case TwoRegisters(MEM_IX_D | MEM_ABS_16 | MEM_ABS_8 | MEM_DE | MEM_BC | MEM_IY_D | MEM_HL, _) => true
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@ -25,7 +25,7 @@ object ZOpcode extends Enumeration {
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DJNZ, JP, JR, CALL, RET, RETN, RETI, HALT,
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//sharp:
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LD_AHLI, LD_AHLD, LD_HLIA, LD_HLDA, SWAP, LDH_DA, LDH_AD, LDH_CA, LDH_AC, LD_HLSP, ADD_SP, STOP,
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DISCARD_A, DISCARD_F, DISCARD_HL, DISCARD_BC, DISCARD_DE, DISCARD_IX, DISCARD_IY,
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DISCARD_A, DISCARD_F, DISCARD_HL, DISCARD_BC, DISCARD_DE, DISCARD_IX, DISCARD_IY, CHANGED_MEM,
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LABEL, BYTE = Value
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}
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@ -196,6 +196,7 @@ object HelperCheckers {
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case OneRegister(MEM_HL | MEM_IX_D | MEM_IY_D | MEM_BC | MEM_DE) => true
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case OneRegister(_) => false
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}
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case CHANGED_MEM => true
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case POP | PUSH => false
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case _ => true // TODO
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}
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15
src/main/scala/millfork/env/Environment.scala
vendored
15
src/main/scala/millfork/env/Environment.scala
vendored
@ -1,9 +1,9 @@
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package millfork.env
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import millfork.assembly.BranchingOpcodeMapping
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import millfork.assembly.{BranchingOpcodeMapping, Elidability}
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import millfork.{env, _}
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import millfork.assembly.mos.Opcode
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import millfork.assembly.z80.{IfFlagClear, IfFlagSet, ZFlag}
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import millfork.assembly.mos.{AddrMode, Opcode}
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import millfork.assembly.z80._
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import millfork.compiler.{AbstractExpressionCompiler, LabelGenerator}
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import millfork.error.Logger
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import millfork.node._
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@ -1300,6 +1300,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
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def collectDeclarations(program: Program, options: CompilationOptions): Unit = {
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val b = get[VariableType]("byte")
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val v = get[Type]("void")
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if (options.flag(CompilationFlag.OptimizeForSonicSpeed)) {
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addThing(InitializedArray("identity$", None, List.tabulate(256)(n => LiteralExpression(n, 1)), declaredBank = None, b, b, defaultArrayAlignment(options, 256)), None)
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}
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@ -1345,6 +1346,14 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
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}
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}
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}
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if (!things.contains("memory_barrier")) {
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things("memory_barrier") = MacroFunction("memory_barrier", v, NormalParamSignature(Nil), this, CpuFamily.forType(options.platform.cpu) match {
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case CpuFamily.M6502 => List(MosAssemblyStatement(Opcode.CHANGED_MEM, AddrMode.DoesNotExist, LiteralExpression(0, 1), Elidability.Fixed))
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case CpuFamily.I80 => List(Z80AssemblyStatement(ZOpcode.CHANGED_MEM, NoRegisters, None, LiteralExpression(0, 1), Elidability.Fixed))
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case _ => ???
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})
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}
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}
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def hintTypo(name: String): Unit = {
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@ -74,9 +74,9 @@ class Z80Assembler(program: Program,
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case ZLine0(BYTE, NoRegisters, param) =>
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writeByte(bank, index, param)
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index + 1
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case ZLine0(DISCARD_F | DISCARD_HL | DISCARD_BC | DISCARD_DE | DISCARD_IX | DISCARD_IY | DISCARD_A, NoRegisters, _) =>
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case ZLine0(DISCARD_F | DISCARD_HL | DISCARD_BC | DISCARD_DE | DISCARD_IX | DISCARD_IY | DISCARD_A | CHANGED_MEM, NoRegisters, _) =>
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index
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case ZLine0(LABEL | BYTE | DISCARD_F | DISCARD_HL | DISCARD_BC | DISCARD_DE | DISCARD_IX | DISCARD_IY | DISCARD_A, _, _) =>
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case ZLine0(LABEL | BYTE | DISCARD_F | DISCARD_HL | DISCARD_BC | DISCARD_DE | DISCARD_IX | DISCARD_IY | DISCARD_A | CHANGED_MEM, _, _) =>
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???
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case ZLine0(RST, NoRegisters, param) =>
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val opcode = param.quickSimplify match {
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