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Optimizations of adding one
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@ -1388,8 +1388,32 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & HasClear(State.D) & DoesntMatterWhatItDoesWith(State.V)) ~~> { code =>
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(Elidable & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & HasClear(State.D) & DoesntMatterWhatItDoesWith(State.V)) ~~> { code =>
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List(code.head, AssemblyLine.implied(ROL))
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List(code.head, AssemblyLine.implied(ROL))
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},
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},
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(Elidable & HasOpcode(ADC) & HasImmediate(0) & HasClear(State.C) & DoesntMatterWhatItDoesWith(State.V, State.C, State.N, State.Z)) ~~> (_ => Nil),
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(Elidable & HasOpcode(ROL) & HasClear(State.C)) ~~> (code => code.map(_.copy(opcode = ASL))),
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(Elidable & HasOpcode(ROL) & HasClear(State.C)) ~~> (code => code.map(_.copy(opcode = ASL))),
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(Elidable & HasOpcode(ROR) & HasClear(State.C)) ~~> (code => code.map(_.copy(opcode = LSR))),
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(Elidable & HasOpcode(ROR) & HasClear(State.C)) ~~> (code => code.map(_.copy(opcode = LSR))),
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(HasOpcode(AND) & HasImmediate(1)) ~
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(Linear & Not(ChangesNAndZ) & Not(HasOpcode(CLC)) & Not(ChangesA)).* ~
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(Elidable & HasOpcode(CLC) & HasClear(State.D)) ~
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(Elidable & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & HasAddrModeIn(Set(ZeroPage, ZeroPageX, Absolute, AbsoluteX))) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.C, State.V, State.Z, State.N, State.A)) ~~> { code =>
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val label = getNextLabel("in")
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code.take(code.length - 3) ++ List(
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AssemblyLine.relative(BEQ, label),
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code.last.copy(opcode = INC),
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AssemblyLine.label(label)
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)
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},
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(HasOpcode(ANC) & HasImmediate(1)) ~
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(Linear & Not(ChangesNAndZ) & Not(ChangesA) & (Not(ChangesC) | HasOpcode(CLC))).* ~
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(Elidable & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & HasClear(State.D) & HasAddrModeIn(Set(ZeroPage, ZeroPageX, Absolute, AbsoluteX))) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.C, State.V, State.Z, State.N, State.A)) ~~> { code =>
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val label = getNextLabel("in")
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code.head.copy(opcode = AND) :: code.take(code.length - 2).tail ++ List(
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AssemblyLine.relative(BEQ, label),
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code.last.copy(opcode = INC),
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AssemblyLine.label(label)
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)
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},
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)
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)
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val IndexSequenceOptimization = new RuleBasedAssemblyOptimization("Index sequence optimization",
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val IndexSequenceOptimization = new RuleBasedAssemblyOptimization("Index sequence optimization",
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@ -1542,6 +1566,19 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcode(ROR) & DoesntMatterWhatItDoesWith(State.N, State.Z, State.C) & MatchAddrMode(0) & MatchParameter(1)) ~~> { code =>
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(Elidable & HasOpcode(ROR) & DoesntMatterWhatItDoesWith(State.N, State.Z, State.C) & MatchAddrMode(0) & MatchParameter(1)) ~~> { code =>
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code.init.last :: code.last :: code.drop(2).init.init
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code.init.last :: code.last :: code.drop(2).init.init
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},
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},
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(Elidable & HasOpcode(ASL) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(INC) & MatchAddrMode(0) & MatchParameter(1)) ~~> { code =>
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List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))
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},
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(Elidable & HasOpcode(ASL) & HasAddrMode(AddrMode.Implied)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { code =>
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List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))
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},
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(Elidable & HasOpcode(ASL) & HasAddrMode(AddrMode.Implied)) ~
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(Elidable & HasOpcodeIn(Set(ORA, EOR)) & HasImmediate(1)) ~~> { code =>
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List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))
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},
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)
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)
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private def blockIsIdempotentWhenItComesToIndexRegisters(i: Int) = Where(ctx => {
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private def blockIsIdempotentWhenItComesToIndexRegisters(i: Int) = Where(ctx => {
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@ -506,4 +506,38 @@ class AssemblyOptimizationSuite extends FunSuite with Matchers {
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m.readByte(0xc000) should equal(0x46)
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m.readByte(0xc000) should equal(0x46)
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}
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}
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}
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}
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test("Shift and increase") {
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EmuBenchmarkRun(
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"""
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| byte output @$c000
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| void main() {
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| output = twicePlusOne(5)
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| }
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| noinline byte twicePlusOne (byte x) {
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| return x * 2 + 1
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| }
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""".stripMargin
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){m =>
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m.readByte(0xc000) should equal(11)
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}
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}
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test("Add one bit") {
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EmuBenchmarkRun(
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"""
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| byte output @$c000
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| void main() {
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| output = 0
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| increaseByBit(5)
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| }
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| noinline void increaseByBit (byte y) {
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| output += y & 1
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| }
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""".stripMargin
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){m =>
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m.readByte(0xc000) should equal(1)
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}
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}
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}
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}
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