From b9eb59ad51661eb7085a8d6cdc464f20cf4f4847 Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Mon, 26 Feb 2018 16:45:01 +0100 Subject: [PATCH] Replace pointless LAX and ANC with their legal equivalents --- .../millfork/assembly/opt/UndocumentedOptimizations.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala b/src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala index cb75bd2f..02e5e8ad 100644 --- a/src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala +++ b/src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala @@ -2,7 +2,7 @@ package millfork.assembly.opt import java.util.concurrent.atomic.AtomicInteger -import millfork.assembly.{AddrMode, AssemblyLine, Opcode, State} +import millfork.assembly._ import millfork.assembly.Opcode._ import millfork.assembly.AddrMode._ import millfork.assembly.OpcodeClasses._ @@ -17,6 +17,7 @@ object UndocumentedOptimizations { def getNextLabel(prefix: String) = f".$prefix%s__${counter.getAndIncrement()}%05d" + private val LdxAddrModes = Set(ZeroPage, Absolute, Immediate, AbsoluteY, ZeroPageY) private val LaxAddrModeRestriction = Not(HasAddrModeIn(Set(AbsoluteX, ZeroPageX, IndexedX, Immediate))) //noinspection ScalaUnnecessaryParentheses @@ -390,6 +391,9 @@ object UndocumentedOptimizations { HasOpcodeIn(Set(TAX, TXA, LAX)) ~ (Elidable & HasOpcode(SBX) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z)) ~~> (code => List(code.head)), HasOpcodeIn(Set(TAX, TXA, LAX)) ~ (Elidable & HasOpcode(SBX) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C)) ~~> (code => List(code.head, AssemblyLine.implied(DEX))), HasOpcodeIn(Set(TAX, TXA, LAX)) ~ (Elidable & HasOpcode(SBX) & HasImmediate(0xff) & DoesntMatterWhatItDoesWith(State.C)) ~~> (code => List(code.head, AssemblyLine.implied(INX))), + (Elidable & HasOpcode(LAX) & DoesntMatterWhatItDoesWith(State.X)) ~~> (_.map(_.copy(opcode = LDA))), + (Elidable & HasOpcode(LAX) & HasAddrModeIn(LdxAddrModes) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.map(_.copy(opcode = LDX))), + (Elidable & HasOpcode(ANC) & DoesntMatterWhatItDoesWith(State.C)) ~~> (_.map(_.copy(opcode = AND))), ) val All: List[AssemblyOptimization] = List(