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6502: more bit-twiddling optimizations
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@ -8,6 +8,7 @@ import millfork.assembly.mos.OpcodeClasses._
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import millfork.assembly.mos.{AddrMode, opt, _}
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import millfork.assembly.mos.AddrMode._
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import millfork.env._
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import millfork.error.FatalErrorReporting
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/**
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* These optimizations should not remove opportunities for more complex optimizations to trigger.
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@ -1598,18 +1599,18 @@ object AlwaysGoodOptimizations {
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val originalStart = if (shiftBeforeStore) {
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(Elidable & HasOpcode(ASL) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(STA) & HasAddrMode(Absolute) & MatchParameter(0)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(0)) ~
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(Elidable & HasOpcode(LDA) & HasImmediate(0)) ~
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(Elidable & HasOpcode(ROL) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(STA) & HasAddrMode(Absolute) & MatchParameter(1))
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(1))
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} else {
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(Elidable & HasOpcode(STA) & HasAddrMode(Absolute) & MatchParameter(0)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(0)) ~
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(Elidable & HasOpcode(LDA) & HasImmediate(0)) ~
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(Elidable & HasOpcode(STA) & HasAddrMode(Absolute) & MatchParameter(1))
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(1))
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}
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val shifting = (0 until shiftAmountAfterStore).map(_ =>
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(Elidable & HasOpcode(ASL) & HasAddrMode(Absolute) & MatchParameter(0)) ~
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(Elidable & HasOpcode(ROL) & HasAddrMode(Absolute) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.N, State.Z, State.A))
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(Elidable & HasOpcode(ASL) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(0)) ~
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(Elidable & HasOpcode(ROL) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.N, State.Z, State.A))
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).reduce(_ ~ _)
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val rightShiftCount = 8 - (if (shiftBeforeStore) shiftAmountAfterStore + 1 else shiftAmountAfterStore)
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@ -2053,6 +2054,24 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcodeIn(ORA, EOR) & HasImmediate(1)) ~~> { code =>
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List(AssemblyLine.implied(SEC), code.head.copy(opcode = ROL))
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},
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(Elidable & HasOpcode(BIT) & DoesntMatterWhatItDoesWith(State.V, State.C, State.Z) & HasAddrModeIn(Absolute, ZeroPage) & MatchAddrMode(2) & MatchParameter(3)) ~
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DebugMatching ~
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(Elidable & HasOpcodeIn(BPL, BMI) & MatchParameter(1)) ~
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DebugMatching ~
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(Linear & DoesNotConcernMemoryAt(2, 3)).* ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(1) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(ASL) & MatchAddrMode(2) & MatchParameter(3)) ~~> { code =>
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List(code.last, remapN2C(code(1))) ++ (code.drop(2).init)
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},
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(Elidable & HasOpcode(LDA) & DoesntMatterWhatItDoesWith(State.A, State.C, State.Z) & HasAddrModeIn(Absolute, ZeroPage) & MatchAddrMode(2) & MatchParameter(3)) ~
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(Elidable & HasOpcodeIn(BPL, BMI) & MatchParameter(1)) ~
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(Linear & DoesNotConcernMemoryAt(2, 3) & Not(ConcernsA)).* ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(1) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(ASL) & MatchAddrMode(2) & MatchParameter(3)) ~~> { code =>
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List(code.last, remapN2C(code(1))) ++ (code.drop(2) :+ code.init.last)
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},
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)
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private def blockIsIdempotentWhenItComesToIndexRegisters(i: Int) = Where(ctx => {
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@ -2233,18 +2252,39 @@ object AlwaysGoodOptimizations {
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},
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)
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private def remapZ2N(line: AssemblyLine) = line.opcode match {
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private def remapZ2N(line: AssemblyLine): AssemblyLine = line.opcode match {
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case BNE => line.copy(opcode = BMI)
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case BEQ => line.copy(opcode = BPL)
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case _ => FatalErrorReporting.reportFlyingPig(s"Tried to treat ${line.opcode} as a branch on Z")
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}
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private def remapZ2V(line: AssemblyLine) = line.opcode match {
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private def remapC2N(line: AssemblyLine): AssemblyLine = line.opcode match {
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case BCS => line.copy(opcode = BMI)
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case BCC => line.copy(opcode = BPL)
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case _ => FatalErrorReporting.reportFlyingPig(s"Tried to treat ${line.opcode} as a branch on C")
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}
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private def remapN2C(line: AssemblyLine): AssemblyLine = line.opcode match {
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case BMI => line.copy(opcode = BCS)
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case BPL => line.copy(opcode = BCC)
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case _ => FatalErrorReporting.reportFlyingPig(s"Tried to treat ${line.opcode} as a branch on N")
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}
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private def remapZ2CInverse(line: AssemblyLine): AssemblyLine = line.opcode match {
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case BNE => line.copy(opcode = BCS)
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case BEQ => line.copy(opcode = BCC)
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case _ => FatalErrorReporting.reportFlyingPig(s"Tried to treat ${line.opcode} as a branch on C")
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}
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private def remapZ2V(line: AssemblyLine): AssemblyLine = line.opcode match {
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case BNE => line.copy(opcode = BVS)
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case BEQ => line.copy(opcode = BVC)
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case _ => FatalErrorReporting.reportFlyingPig(s"Tried to treat ${line.opcode} as a branch on Z")
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}
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val SimplifiableCondition = new RuleBasedAssemblyOptimization("Simplifiable condition",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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HasOpcode(LDA) ~
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HasOpcodeIn(LDA, TXA, TYA, TZA, ADC, SBC, AND, ORA, EOR) ~
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(Elidable & HasOpcode(AND) & HasImmediate(0x80)) ~
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(Elidable & HasOpcodeIn(BNE, BEQ) & DoesntMatterWhatItDoesWith(State.A, State.N, State.Z)) ~~> {code =>
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List(code(0), remapZ2N(code(2)))
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@ -2254,6 +2294,16 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcodeIn(BNE, BEQ) & DoesntMatterWhatItDoesWith(State.A, State.N, State.Z)) ~~> {code =>
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List(code(1).copy(opcode = LDA), remapZ2N(code(2)))
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},
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HasOpcodeIn(LDA, TXA, TYA, TZA, ADC, SBC, AND, ORA, EOR) ~
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(Elidable & HasOpcode(ASL)) ~
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(Elidable & HasOpcodeIn(BCS, BCC) & DoesntMatterWhatItDoesWith(State.A, State.N, State.C, State.Z)) ~~> {code =>
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List(code(0), remapC2N(code(2)))
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},
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(HasOpcodeIn(LDA, AND) & HasImmediate(0)) ~
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(Elidable & HasOpcode(ROL)) ~
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(Elidable & HasOpcodeIn(BEQ, BNE) & DoesntMatterWhatItDoesWith(State.A, State.N, State.C, State.Z)) ~~> {code =>
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List(code(0), remapZ2CInverse(code(2)))
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},
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)
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val PointlessSignCheck: RuleBasedAssemblyOptimization = {
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@ -824,7 +824,7 @@ case object ReadsY extends TrivialAssemblyLinePattern {
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case object ConcernsC extends TrivialAssemblyLinePattern {
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override def apply(line: AssemblyLine): Boolean =
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OpcodeClasses.ReadsC(line.opcode) && OpcodeClasses.ChangesC(line.opcode)
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OpcodeClasses.ReadsC(line.opcode) || OpcodeClasses.ChangesC(line.opcode)
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}
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case object ConcernsA extends TrivialAssemblyLinePattern {
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@ -307,6 +307,33 @@ object ZeropageRegisterOptimizations {
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})
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)
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val SimplifiableAddingOfOneBit = new RuleBasedAssemblyOptimization("Simplifiable adding of one bit",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(AND) & HasImmediate(1)) ~
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(Elidable & HasOpcode(STA) & RefersTo("__reg", 0) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.A, State.N, State.Z, State.C)) ~
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(Linear & Not(ConcernsC) & DoesNotConcernMemoryAt(0, 1)).*.capture(5) ~
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(Elidable & HasOpcode(ASL) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasClear(State.D) & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.V)) ~~> { (code, ctx) =>
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AssemblyLine.implied(ROR) :: (ctx.get[List[AssemblyLine]](5) :+ AssemblyLine.implied(ROL))
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},
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(Elidable & HasOpcode(ASL) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(STA) & RefersTo("__reg", 0) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.A, State.N, State.Z, State.C)) ~
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(Linear & Not(HasOpcode(AND)) & Not(ConcernsC) & DoesNotConcernMemoryAt(0, 1)).*.capture(5) ~
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(Elidable & HasOpcode(AND) & HasImmediate(1)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasClear(State.D) & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.V)) ~~> { (code, ctx) =>
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code(1) :: (ctx.get[List[AssemblyLine]](5) ++ List(AssemblyLine.implied(ROR), code(1).copy(opcode = LDA), AssemblyLine.implied(ROL)))
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},
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(Elidable & HasOpcode(ASL) & HasAddrMode(Implied)) ~
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(Elidable & HasOpcode(STA) & RefersTo("__reg", 0) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.A, State.N, State.Z, State.C)) ~
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(Linear & Not(HasOpcode(ANC)) & Not(ConcernsC) & DoesNotConcernMemoryAt(0, 1)).*.capture(5) ~
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(Elidable & HasOpcode(ANC) & HasImmediate(1)) ~
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(Elidable & HasClear(State.D) & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.V)) ~~> { (code, ctx) =>
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code(1) :: (ctx.get[List[AssemblyLine]](5) ++ List(AssemblyLine.implied(ROR), code(1).copy(opcode = LDA), AssemblyLine.implied(ROL)))
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},
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)
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val All: List[AssemblyOptimization[AssemblyLine]] = List(
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ConstantDecimalMath,
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ConstantMultiplication,
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@ -315,6 +342,7 @@ object ZeropageRegisterOptimizations {
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DeadRegStore,
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DeadRegStoreFromFlow,
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PointlessLoad,
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SimplifiableAddingOfOneBit,
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StashInRegInsteadOfStack,
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)
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@ -562,4 +562,55 @@ class AssemblyOptimizationSuite extends FunSuite with Matchers {
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}
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}
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test("Shift, mask and increase 1") {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos)(
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"""
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| byte output @$c000
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| void main() {
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| output = twicePlusLowBit(5, 5)
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| }
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| noinline byte twicePlusLowBit (byte x, byte y) {
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| return (y & 1) + x * 2
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| }
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""".stripMargin
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) { m =>
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m.readByte(0xc000) should equal(11)
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}
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}
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test("Shift, mask and increase 2") {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos)(
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"""
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| byte output @$c000
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| void main() {
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| output = twicePlusLowBit(5, 5)
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| }
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| noinline byte twicePlusLowBit (byte x, byte y) {
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| return x * 2 + (y & 1)
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| }
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""".stripMargin
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) { m =>
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m.readByte(0xc000) should equal(11)
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}
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}
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test("Shift, mask, increase and test") {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos)(
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"""
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| byte output @$c000
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| void main() {
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| stuff(0, 4)
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| }
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| inline void stuff (byte x, byte y) {
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| if ((f(y) & 1) + x * 2) == 0 {
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| output = 11
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| }
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| }
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| noinline byte f(byte y) { return y }
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""".stripMargin
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) { m =>
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m.readByte(0xc000) should equal(11)
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}
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}
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}
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@ -39,6 +39,26 @@ class BitPackingSuite extends FunSuite with Matchers {
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}
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}
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test("Population count") {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos)("""
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| byte output @$c000
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| noinline byte popcnt(byte x) {
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| byte result
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| result = 0
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| while x != 0 {
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| if x & $80 != 0 { result += 1 }
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| x <<= 1
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| }
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| return result
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| }
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| void main () {
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| output = popcnt(5)
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| }
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""".stripMargin){m =>
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m.readByte(0xc000) should equal(2)
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}
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}
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test("Unpack bits from a word") {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Sharp)("""
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| array output[16]
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