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LAX optimization bugfix

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This commit is contained in:
Karol Stasiak 2018-03-09 17:33:56 +01:00
parent 871143cc21
commit bf851af2e4
1 changed files with 12 additions and 12 deletions
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24
src/main/scala/millfork/assembly/opt/UndocumentedOptimizations.scala
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@ -24,45 +24,45 @@ object UndocumentedOptimizations {
val UseLax = new RuleBasedAssemblyOptimization("Using undocumented instruction LAX",
needsFlowInfo = FlowInfoRequirement.BackwardFlow,
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesMemory) & Not(HasOpcode(LDX))).*.capture(2) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesMemory) & Not(HasOpcode(LDX)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
ctx.get[List[AssemblyLine]](2) :+ code.head.copy(opcode = LAX)
},
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & MatchParameter(1) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesMemory) & Not(HasOpcode(LDA))).*.capture(2) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesMemory) & Not(HasOpcode(LDA)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
ctx.get[List[AssemblyLine]](2) :+ code.head.copy(opcode = LAX)
},
(HasOpcode(LDA) & Elidable & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesMemory) & Not(HasOpcode(TAX))).*.capture(2) ~
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesMemory) & Not(HasOpcode(TAX)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(TAX) & Elidable) ~~> { (code, ctx) =>
ctx.get[List[AssemblyLine]](2) :+ code.head.copy(opcode = LAX)
},
(HasOpcode(LDX) & Elidable & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesMemory) & Not(HasOpcode(TXA))).*.capture(2) ~
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesMemory) & Not(HasOpcode(TXA)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(TXA) & Elidable) ~~> { (code, ctx) =>
ctx.get[List[AssemblyLine]](2) :+ code.head.copy(opcode = LAX)
},
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesA) & Not(ChangesMemory) & Not(HasOpcode(LDX))).*.capture(2) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesA) & Not(ChangesMemory) & Not(HasOpcode(LDX)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> { (code, ctx) =>
code.head.copy(opcode = LAX) :: ctx.get[List[AssemblyLine]](2)
},
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & MatchParameter(1) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesX) & Not(ChangesMemory) & Not(HasOpcode(LDA))).*.capture(2) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesX) & Not(ChangesMemory) & Not(HasOpcode(LDA)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & MatchParameter(1) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> { (code, ctx) =>
code.head.copy(opcode = LAX) :: ctx.get[List[AssemblyLine]](2)
},
(HasOpcode(LDA) & Elidable & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesA) & Not(ChangesMemory) & Not(HasOpcode(TAX))).*.capture(2) ~
(HasOpcode(LDA) & Elidable & MatchAddrMode(0) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsX) & Not(ChangesA) & Not(ChangesMemory) & Not(HasOpcode(TAX)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(TAX) & Elidable & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> { (code, ctx) =>
code.head.copy(opcode = LAX) :: ctx.get[List[AssemblyLine]](2)
},
(HasOpcode(LDX) & Elidable & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesX) & Not(ChangesMemory) & Not(HasOpcode(TXA))).*.capture(2) ~
(HasOpcode(LDX) & Elidable & MatchAddrMode(0) & LaxAddrModeRestriction) ~
(LinearOrLabel & Not(ConcernsA) & Not(ChangesX) & Not(ChangesMemory) & Not(HasOpcode(TXA)) & DoesntChangeIndexingInAddrMode(0)).*.capture(2) ~
(HasOpcode(TXA) & Elidable & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> { (code, ctx) =>
code.head.copy(opcode = LAX) :: ctx.get[List[AssemblyLine]](2)
},