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Fix the zp_reg module

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This commit is contained in:
Karol Stasiak 2019-06-28 17:57:26 +02:00
parent 13c23c1bd1
commit c6d3cefa26
2 changed files with 55 additions and 55 deletions
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68
include/init_rw_memory.mfk
View File

@ -8,14 +8,14 @@
#if TINY_RW_MEMORY
noinline asm void init_rw_memory() {
ldx #__rwdata_size.lo // can't be more than $00FC
beq __init_rw_memory__skip3
? ldx #__rwdata_size.lo // can't be more than $00FC
? beq __init_rw_memory__skip3
+ memory_barrier()
__init_rw_memory__loop3:
lda lo(__rwdata_init_start - 1),x
sta lo(__rwdata_start - 1),x
dex
bne __init_rw_memory__loop3
? lda lo(__rwdata_init_start - 1),x
? sta lo(__rwdata_start - 1),x
? dex
? bne __init_rw_memory__loop3
+ memory_barrier()
__init_rw_memory__skip3:
rts
@ -28,43 +28,43 @@ __init_rw_memory__skip3:
#endif
noinline asm void init_rw_memory() {
lda #__rwdata_size.hi
ora #__rwdata_size.lo
beq __init_rw_memory__skip3
? lda #__rwdata_size.hi
? ora #__rwdata_size.lo
? beq __init_rw_memory__skip3
+ memory_barrier()
ldx #__rwdata_size.hi
beq __init_rw_memory__skip1
? ldx #__rwdata_size.hi
? beq __init_rw_memory__skip1
lda #__rwdata_init_start.lo
sta lo(__reg)
lda #__rwdata_init_start.hi
sta lo(__reg + 1)
lda #__rwdata_start.lo
sta lo(__reg + 2)
lda #__rwdata_start.hi
sta lo(__reg + 3)
? lda #__rwdata_init_start.lo
? sta __reg
? lda #__rwdata_init_start.hi
? sta __reg+1
? lda #__rwdata_start.lo
? sta __reg+2
? lda #__rwdata_start.hi
? sta __reg+3
__init_rw_memory__loop1:
ldy #0
? ldy #0
__init_rw_memory__loop2:
lda (lo(__reg)),y
sta (lo(__reg + 2)),y
dey
bne __init_rw_memory__loop2
inc lo(__reg + 1)
inc lo(__reg + 3)
dex
bne __init_rw_memory__loop1
? lda (__reg),y
? sta (__reg+2),y
? dey
? bne __init_rw_memory__loop2
? inc __reg+1
? inc __reg+3
? dex
? bne __init_rw_memory__loop1
__init_rw_memory__skip1:
ldx #__rwdata_size.lo
beq __init_rw_memory__skip3
? ldx #__rwdata_size.lo
? beq __init_rw_memory__skip3
__init_rw_memory__loop3:
lda __rwdata_init_start + (__rwdata_size & $ff00) - 1,x
sta __rwdata_start + (__rwdata_size & $ff00) - 1,x
dex
bne __init_rw_memory__loop3
? lda __rwdata_init_start + (__rwdata_size & $ff00) - 1,x
? sta __rwdata_start + (__rwdata_size & $ff00) - 1,x
? dex
? bne __init_rw_memory__loop3
__init_rw_memory__skip3:
+ memory_barrier()
rts

42
include/zp_reg.mfk
View File

@ -8,11 +8,11 @@ noinline asm byte __mul_u8u8u8() {
? JMP __mul_u8u8u8_start
__mul_u8u8u8_add:
? CLC
? ADC lo(__reg)
? ADC __reg
__mul_u8u8u8_loop:
? ASL lo(__reg)
? ASL __reg
__mul_u8u8u8_start:
? LSR lo(__reg+1)
? LSR __reg+1
? BCS __mul_u8u8u8_add
? BNE __mul_u8u8u8_loop
? RTS
@ -25,21 +25,21 @@ noinline asm byte __mod_u8u8u8u8() {
? LDX #7
? CLC
__divmod_u8u8u8u8_start:
? ROL lo(__reg)
? ROL __reg
? ROL
? CMP lo(__reg+1)
? CMP __reg+1
? BCC __divmod_u8u8u8u8_skip
? SBC lo(__reg+1)
? SBC __reg+1
__divmod_u8u8u8u8_skip:
? DEX
? BPL __divmod_u8u8u8u8_start
? ROL lo(__reg)
? ROL __reg
? RTS
}
asm byte __div_u8u8u8u8() {
? JSR __mod_u8u8u8u8
? LDA lo(__reg)
? LDA __reg
? RTS
}
@ -51,17 +51,17 @@ noinline asm word __mul_u16u8u16() {
? JMP __mul_u16u8u16_start
__mul_u16u8u16_add:
? CLC
? ADC lo(__reg)
? ADC __reg
? TAY
? TXA
? ADC lo(__reg+1)
? ADC __reg+1
? TAX
? TYA
__mul_u16u8u16_loop:
? ASL lo(__reg)
? ROL lo(__reg+1)
? ASL __reg
? ROL __reg+1
__mul_u16u8u16_start:
? LSR lo(__reg+2)
? LSR __reg+2
? BCS __mul_u16u8u16_add
? BNE __mul_u16u8u16_loop
? RTS
@ -74,24 +74,24 @@ noinline asm byte __mod_u16u8u16u8() {
? LDX #15
? CLC
__divmod_u16u8u16u8_start:
? ROL lo(__reg)
? ROL lo(__reg+1)
? ROL __reg
? ROL __reg+1
? ROL
? CMP lo(__reg+2)
? CMP __reg+2
? BCC __divmod_u16u8u16u8_skip
? SBC lo(__reg+2)
? SBC __reg+2
__divmod_u16u8u16u8_skip:
? DEX
? BPL __divmod_u16u8u16u8_start
? ROL lo(__reg)
? ROL lo(__reg+1)
? ROL __reg
? ROL __reg+1
? RTS
}
asm word __div_u16u8u16u8() {
? JSR __mod_u16u8u16u8
? LDA lo(__reg)
? LDX lo(__reg+1)
? LDA __reg
? LDX __reg+1
? RTS
}