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Fix the zp_reg module

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This commit is contained in:
Karol Stasiak 2019-06-28 17:57:26 +02:00
parent 13c23c1bd1
commit c6d3cefa26
2 changed files with 55 additions and 55 deletions
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68
include/init_rw_memory.mfk
View File

@ -8,14 +8,14 @@
#if TINY_RW_MEMORY #if TINY_RW_MEMORY
noinline asm void init_rw_memory() { noinline asm void init_rw_memory() {
ldx #__rwdata_size.lo // can't be more than $00FC ? ldx #__rwdata_size.lo // can't be more than $00FC
beq __init_rw_memory__skip3 ? beq __init_rw_memory__skip3
+ memory_barrier() + memory_barrier()
__init_rw_memory__loop3: __init_rw_memory__loop3:
lda lo(__rwdata_init_start - 1),x ? lda lo(__rwdata_init_start - 1),x
sta lo(__rwdata_start - 1),x ? sta lo(__rwdata_start - 1),x
dex ? dex
bne __init_rw_memory__loop3 ? bne __init_rw_memory__loop3
+ memory_barrier() + memory_barrier()
__init_rw_memory__skip3: __init_rw_memory__skip3:
rts rts
@ -28,43 +28,43 @@ __init_rw_memory__skip3:
#endif #endif
noinline asm void init_rw_memory() { noinline asm void init_rw_memory() {
lda #__rwdata_size.hi ? lda #__rwdata_size.hi
ora #__rwdata_size.lo ? ora #__rwdata_size.lo
beq __init_rw_memory__skip3 ? beq __init_rw_memory__skip3
+ memory_barrier() + memory_barrier()
ldx #__rwdata_size.hi ? ldx #__rwdata_size.hi
beq __init_rw_memory__skip1 ? beq __init_rw_memory__skip1
lda #__rwdata_init_start.lo ? lda #__rwdata_init_start.lo
sta lo(__reg) ? sta __reg
lda #__rwdata_init_start.hi ? lda #__rwdata_init_start.hi
sta lo(__reg + 1) ? sta __reg+1
lda #__rwdata_start.lo ? lda #__rwdata_start.lo
sta lo(__reg + 2) ? sta __reg+2
lda #__rwdata_start.hi ? lda #__rwdata_start.hi
sta lo(__reg + 3) ? sta __reg+3
__init_rw_memory__loop1: __init_rw_memory__loop1:
ldy #0 ? ldy #0
__init_rw_memory__loop2: __init_rw_memory__loop2:
lda (lo(__reg)),y ? lda (__reg),y
sta (lo(__reg + 2)),y ? sta (__reg+2),y
dey ? dey
bne __init_rw_memory__loop2 ? bne __init_rw_memory__loop2
inc lo(__reg + 1) ? inc __reg+1
inc lo(__reg + 3) ? inc __reg+3
dex ? dex
bne __init_rw_memory__loop1 ? bne __init_rw_memory__loop1
__init_rw_memory__skip1: __init_rw_memory__skip1:
ldx #__rwdata_size.lo ? ldx #__rwdata_size.lo
beq __init_rw_memory__skip3 ? beq __init_rw_memory__skip3
__init_rw_memory__loop3: __init_rw_memory__loop3:
lda __rwdata_init_start + (__rwdata_size & $ff00) - 1,x ? lda __rwdata_init_start + (__rwdata_size & $ff00) - 1,x
sta __rwdata_start + (__rwdata_size & $ff00) - 1,x ? sta __rwdata_start + (__rwdata_size & $ff00) - 1,x
dex ? dex
bne __init_rw_memory__loop3 ? bne __init_rw_memory__loop3
__init_rw_memory__skip3: __init_rw_memory__skip3:
+ memory_barrier() + memory_barrier()
rts rts

42
include/zp_reg.mfk
View File

@ -8,11 +8,11 @@ noinline asm byte __mul_u8u8u8() {
? JMP __mul_u8u8u8_start ? JMP __mul_u8u8u8_start
__mul_u8u8u8_add: __mul_u8u8u8_add:
? CLC ? CLC
? ADC lo(__reg) ? ADC __reg
__mul_u8u8u8_loop: __mul_u8u8u8_loop:
? ASL lo(__reg) ? ASL __reg
__mul_u8u8u8_start: __mul_u8u8u8_start:
? LSR lo(__reg+1) ? LSR __reg+1
? BCS __mul_u8u8u8_add ? BCS __mul_u8u8u8_add
? BNE __mul_u8u8u8_loop ? BNE __mul_u8u8u8_loop
? RTS ? RTS
@ -25,21 +25,21 @@ noinline asm byte __mod_u8u8u8u8() {
? LDX #7 ? LDX #7
? CLC ? CLC
__divmod_u8u8u8u8_start: __divmod_u8u8u8u8_start:
? ROL lo(__reg) ? ROL __reg
? ROL ? ROL
? CMP lo(__reg+1) ? CMP __reg+1
? BCC __divmod_u8u8u8u8_skip ? BCC __divmod_u8u8u8u8_skip
? SBC lo(__reg+1) ? SBC __reg+1
__divmod_u8u8u8u8_skip: __divmod_u8u8u8u8_skip:
? DEX ? DEX
? BPL __divmod_u8u8u8u8_start ? BPL __divmod_u8u8u8u8_start
? ROL lo(__reg) ? ROL __reg
? RTS ? RTS
} }
asm byte __div_u8u8u8u8() { asm byte __div_u8u8u8u8() {
? JSR __mod_u8u8u8u8 ? JSR __mod_u8u8u8u8
? LDA lo(__reg) ? LDA __reg
? RTS ? RTS
} }
@ -51,17 +51,17 @@ noinline asm word __mul_u16u8u16() {
? JMP __mul_u16u8u16_start ? JMP __mul_u16u8u16_start
__mul_u16u8u16_add: __mul_u16u8u16_add:
? CLC ? CLC
? ADC lo(__reg) ? ADC __reg
? TAY ? TAY
? TXA ? TXA
? ADC lo(__reg+1) ? ADC __reg+1
? TAX ? TAX
? TYA ? TYA
__mul_u16u8u16_loop: __mul_u16u8u16_loop:
? ASL lo(__reg) ? ASL __reg
? ROL lo(__reg+1) ? ROL __reg+1
__mul_u16u8u16_start: __mul_u16u8u16_start:
? LSR lo(__reg+2) ? LSR __reg+2
? BCS __mul_u16u8u16_add ? BCS __mul_u16u8u16_add
? BNE __mul_u16u8u16_loop ? BNE __mul_u16u8u16_loop
? RTS ? RTS
@ -74,24 +74,24 @@ noinline asm byte __mod_u16u8u16u8() {
? LDX #15 ? LDX #15
? CLC ? CLC
__divmod_u16u8u16u8_start: __divmod_u16u8u16u8_start:
? ROL lo(__reg) ? ROL __reg
? ROL lo(__reg+1) ? ROL __reg+1
? ROL ? ROL
? CMP lo(__reg+2) ? CMP __reg+2
? BCC __divmod_u16u8u16u8_skip ? BCC __divmod_u16u8u16u8_skip
? SBC lo(__reg+2) ? SBC __reg+2
__divmod_u16u8u16u8_skip: __divmod_u16u8u16u8_skip:
? DEX ? DEX
? BPL __divmod_u16u8u16u8_start ? BPL __divmod_u16u8u16u8_start
? ROL lo(__reg) ? ROL __reg
? ROL lo(__reg+1) ? ROL __reg+1
? RTS ? RTS
} }
asm word __div_u16u8u16u8() { asm word __div_u16u8u16u8() {
? JSR __mod_u16u8u16u8 ? JSR __mod_u16u8u16u8
? LDA lo(__reg) ? LDA __reg
? LDX lo(__reg+1) ? LDX __reg+1
? RTS ? RTS
} }