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Z80: Optimize 16-bit loads after 8-bit stores

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Karol Stasiak 2019-03-18 20:12:33 +01:00
parent 6f00cacc6d
commit c829c5eb37
1 changed files with 13 additions and 0 deletions
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13
src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
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@ -118,6 +118,19 @@ object AlwaysGoodI80Optimizations {
(Elidable & Is16BitLoad(ZRegister.HL, ZRegister.MEM_ABS_16) & MatchParameter(0)) ~~> { (code, ctx) =>
code.init :+ ZLine.ldImm16(ZRegister.HL, ctx.get[Constant](2))
},
for5LargeRegisters(register =>
(Is8BitLoad(MEM_ABS_8, ZRegister.A) & MatchParameter(0) & MatchRegister(A, 2)).captureLine(1) ~
(Linear & DoesntChangeMemoryAt(1) & Not(Is8BitLoad(MEM_ABS_8, ZRegister.A))).* ~
(Is8BitLoad(MEM_ABS_8, ZRegister.A) & MatchParameter(10) & MatchRegister(A, 12)).captureLine(11) ~
Where(ctx => ctx.get[Constant](0).succ == ctx.get[Constant](10)) ~
(Linear & DoesntChangeMemoryAt(1) & DoesntChangeMemoryAt(11)).* ~
(Elidable & Is16BitLoad(register, MEM_ABS_16) & MatchParameter(0) & MatchRegister(A, 12)) ~~> { (code, ctx) =>
val hi = ctx.get[Int](12)
val lo = ctx.get[Int](2)
code.init :+ ZLine.ldImm16(register, hi.<<(8) + lo)
}
),
)
val PointlessLoad = new RuleBasedAssemblyOptimization("Pointless load",