From ca7166d1ae29a081eefbddf17c341675147ce9dc Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Fri, 27 Jan 2023 18:16:02 +0100
Subject: [PATCH] oops

---
 .../mos/opt/IdentityPageOptimizations.scala   | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 src/main/scala/millfork/assembly/mos/opt/IdentityPageOptimizations.scala

diff --git a/src/main/scala/millfork/assembly/mos/opt/IdentityPageOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/IdentityPageOptimizations.scala
new file mode 100644
index 00000000..4ba6f9e8
--- /dev/null
+++ b/src/main/scala/millfork/assembly/mos/opt/IdentityPageOptimizations.scala
@@ -0,0 +1,50 @@
+package millfork.assembly.mos.opt
+
+import millfork.assembly.mos.AddrMode._
+import millfork.assembly.mos.{AssemblyLine, State}
+import millfork.assembly.mos.Opcode._
+import millfork.env.NumericConstant
+
+object IdentityPageOptimizations {
+
+  val SimplifiableAccess = new RuleBasedAssemblyOptimization("Simplifiable identity page access",
+    needsFlowInfo = FlowInfoRequirement.NoRequirement,
+    (Elidable & HasOpcode(LDA) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~~> { c =>
+      List(AssemblyLine.implied(TXA))
+    },
+    (Elidable & HasOpcode(LDA) & HasAddrMode(AbsoluteY) & HasIdentityPageParameter) ~~> { c =>
+      List(AssemblyLine.implied(TYA))
+    },
+  )
+
+  val UseInsteadOfStack = new RuleBasedAssemblyOptimization("Use identity page instead of stack",
+    needsFlowInfo = FlowInfoRequirement.BackwardFlow,
+    (Elidable & HasOpcode(PHA)) ~
+      (Not(ConcernsX) & Not(ConcernsStack)).*.capture(0) ~
+      (Elidable & HasOpcode(TSX) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~
+      (Elidable & HasAddrMode(AbsoluteX) & HasParameterWhere{
+        case NumericConstant(0x101, _) => true
+        case _ => false
+      }).capture(1) ~
+      (Elidable & HasOpcode(INX)) ~
+      (Elidable & HasOpcode(TXS) & DoesntMatterWhatItDoesWith(State.X)) ~~> { (code, ctx) =>
+      List(AssemblyLine.implied(TAX)) ++ ctx.get[List[AssemblyLine]](0) ++ List(ctx.get[AssemblyLine](1).copy(parameter = ctx.identityPage))
+    },
+    (Elidable & HasOpcode(PHA)) ~
+      (Not(ConcernsY) & Not(ConcernsStack)).*.capture(0) ~
+      (Elidable & HasOpcode(TSX) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~
+      (Elidable & HasAddrMode(AbsoluteX) & HasParameterWhere{
+        case NumericConstant(0x101, _) => true
+        case _ => false
+      }).capture(1) ~
+      (Elidable & HasOpcode(INX)) ~
+      (Elidable & HasOpcode(TXS) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx) =>
+      List(AssemblyLine.implied(TAY)) ++ ctx.get[List[AssemblyLine]](0) ++ List(ctx.get[AssemblyLine](1).copy(parameter = ctx.identityPage, addrMode = AbsoluteY))
+    },
+  )
+
+  val All: List[RuleBasedAssemblyOptimization] = List(
+    SimplifiableAccess,
+    UseInsteadOfStack)
+
+}