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More optimizations
This commit is contained in:
Karol Stasiak
parent
54e7139e84
commit
d6f38ba87b
@ -14,6 +14,7 @@ object OptimizationPresets {
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UnusedGlobalVariables,
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)
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val AssOpt: List[AssemblyOptimization] = List[AssemblyOptimization](
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AlwaysGoodOptimizations.NonetAddition,
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AlwaysGoodOptimizations.PointlessSignCheck,
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AlwaysGoodOptimizations.PoinlessLoadBeforeAnotherLoad,
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AlwaysGoodOptimizations.PointlessLoadAfterLoadOrStore,
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@ -31,6 +32,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.PointlessLoadBeforeTransfer,
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VariableToRegisterOptimization,
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AlwaysGoodOptimizations.PoinlessLoadBeforeAnotherLoad,
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AlwaysGoodOptimizations.CommonIndexSubexpressionElimination,
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AlwaysGoodOptimizations.PointlessOperationPairRemoval,
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AlwaysGoodOptimizations.PointlessOperationPairRemoval2,
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AlwaysGoodOptimizations.PoinlessLoadBeforeAnotherLoad,
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@ -125,6 +127,7 @@ object OptimizationPresets {
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DangerousOptimizations.ConstantIndexOffsetPropagation,
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AlwaysGoodOptimizations.CommonBranchBodyOptimization,
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AlwaysGoodOptimizations.CommonExpressionInConditional,
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AlwaysGoodOptimizations.CommonIndexSubexpressionElimination,
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AlwaysGoodOptimizations.ConstantFlowAnalysis,
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AlwaysGoodOptimizations.ConstantIndexPropagation,
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AlwaysGoodOptimizations.DoubleJumpSimplification,
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@ -137,6 +140,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.IndexSequenceOptimization,
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AlwaysGoodOptimizations.MathOperationOnTwoIdenticalMemoryOperands,
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AlwaysGoodOptimizations.ModificationOfJustWrittenValue,
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AlwaysGoodOptimizations.NonetAddition,
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AlwaysGoodOptimizations.OperationsAroundShifting,
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AlwaysGoodOptimizations.PoinlessFlagChange,
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AlwaysGoodOptimizations.PointlessLoadAfterLoadOrStore,
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@ -1220,4 +1220,93 @@ object AlwaysGoodOptimizations {
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(Elidable & HasOpcode(BPL)) ~~> { code => code.init :+ code.last.copy(opcode = JMP, addrMode = Absolute) },
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)
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}
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val NonetAddition = new RuleBasedAssemblyOptimization("Nonet addition",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(LDX) & HasImmediate(0) & HasClear(State.D)) ~
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(Elidable & HasOpcode(BCC) & MatchParameter(14)) ~
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(Elidable & HasOpcode(INX)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(14) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
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(Elidable & HasOpcode(TXA)) ~
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(Elidable & HasOpcode(ADC) & MatchAddrMode(2) & MatchParameter(3) & Not(ConcernsX) & DoesNotConcernMemoryAt(0, 1)) ~
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(Elidable & HasOpcode(STA) & MatchAddrMode(2) & MatchParameter(3) & Not(ConcernsX) & DoesntMatterWhatItDoesWith(State.C, State.N, State.V, State.Z)) ~~> { (code, ctx) =>
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val label = getNextLabel("in")
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List(
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code(1), // BCC
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code(8).copy(opcode = INC),
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code(3), //LABEL
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code(4), //CLC
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code(5), //ADC
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code(6), //STA
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AssemblyLine.relative(BCC, label),
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code(8).copy(opcode = INC),
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AssemblyLine.label(label))
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}
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)
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val CommonIndexSubexpressionElimination: RuleBasedAssemblyOptimization = {
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def eliminate(firstLda: Boolean, targetY: Boolean): AssemblyRule = {
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val firstLoad = HasClear(State.D) & (
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if (firstLda) HasOpcodeIn(Set(LDA, STA, LAX)) & HasAddrModeIn(Set(Absolute, ZeroPage, Immediate)) & MatchParameter(1)
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else if (targetY) HasOpcodeIn(Set(TXA, TAX))
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else HasOpcodeIn(Set(TAY, TYA))
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)
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val secondLoad = Elidable & (
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if (firstLda) HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage, Immediate)) & MatchParameter(1)
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else if (targetY) HasOpcode(TXA)
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else HasOpcode(TYA)
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)
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val firstTransfer = if (targetY) HasOpcode(TAY) else HasOpcode(TAX)
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val secondTransfer = Elidable & (
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if (targetY) HasOpcode(TAY)
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else HasOpcode(TAX)
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) & DoesntMatterWhatItDoesWith(State.A, State.Z, State.N, State.C)
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val fillerLine =
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HasAddrMode(Implied) & HasOpcodeIn(Set(ASL, CLC, CLD, SEC, SED, LSR, INC, DEC)) |
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HasOpcodeIn(Set(ADC, ORA, EOR, AND, SBC)) & HasAddrModeIn(Set(Absolute, ZeroPage, Immediate))
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val firstFiller = fillerLine.*
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val secondFiller = (Elidable & fillerLine).*
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val betweenLines = (Linear & Not(secondLoad)).+
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(firstLoad ~ firstFiller ~ firstTransfer).capture(91) ~ betweenLines.capture(95) ~ (secondLoad ~ secondFiller ~ secondTransfer).capture(92) ~ Where(ctx => {
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val first = ctx.get[List[AssemblyLine]](91)
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val second = ctx.get[List[AssemblyLine]](92)
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val between = ctx.get[List[AssemblyLine]](95)
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var currentD = false
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var currentCDefined = false
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first.length == second.length &&
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first.head.parameter == second.head.parameter &&
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(first.head.addrMode == Immediate) == (second.head.addrMode == Immediate) && first.tail.zip(second.tail).forall(p => {
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p._1.opcode == p._2.opcode && p._1.parameter.quickSimplify == p._2.parameter.quickSimplify && (p._1.addrMode == Immediate) == (p._2.addrMode == Immediate)
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}) && (for (s1 <- first; s2 <- between) yield HelperCheckers.memoryAccessDoesntOverlap(s1.addrMode, s1.parameter, s2.addrMode, s2.parameter)).forall(identity) && {
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var currentD = false
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var currentCDefined = false
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var noAdditionDependency = true
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first.tail.map(_.opcode).foreach{
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case SED => currentD = true
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case CLD => currentD = false
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case CLC | SEC => currentCDefined = true
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case ADC | SBC => noAdditionDependency = currentCDefined
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case _ => ()
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}
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noAdditionDependency && !currentD
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}
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}) ~~> { (code, ctx) =>
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val first = ctx.get[List[AssemblyLine]](91)
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val between = ctx.get[List[AssemblyLine]](95)
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first ++ between
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}
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}
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new RuleBasedAssemblyOptimization("Common index subexpression elimination",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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eliminate(firstLda = true, targetY = false),
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eliminate(firstLda = false, targetY = false),
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eliminate(firstLda = false, targetY = true),
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eliminate(firstLda = true, targetY = true),
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)
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}
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}
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@ -170,13 +170,14 @@ trait AssemblyPattern {
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def captureLength(i: Int) = CaptureLength(i, this)
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protected def memoryAccessDoesntOverlap(a1: AddrMode.Value, p1: Constant, a2: AddrMode.Value, p2: Constant): Boolean = {
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import AddrMode._
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val badAddrModes = Set(IndexedX, IndexedY, ZeroPageIndirect, AbsoluteIndexedX)
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}
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object HelperCheckers {
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import AddrMode._
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private val badAddrModes = Set(IndexedX, IndexedY, ZeroPageIndirect, AbsoluteIndexedX)
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private val goodAddrModes = Set(Implied, Immediate, Relative)
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def memoryAccessDoesntOverlap(a1: AddrMode.Value, p1: Constant, a2: AddrMode.Value, p2: Constant): Boolean = {
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if (badAddrModes(a1) || badAddrModes(a2)) return false
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val goodAddrModes = Set(Implied, Immediate, Relative)
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if (goodAddrModes(a1) || goodAddrModes(a2)) return true
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def handleKnownDistance(distance: Short): Boolean = {
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val indexingAddrModes = Set(AbsoluteIndexedX, AbsoluteX, ZeroPageX, AbsoluteY, ZeroPageY)
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val a1Indexing = indexingAddrModes(a1)
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@ -412,7 +413,7 @@ case class WhereNoMemoryAccessOverlapBetweenTwoLineLists(ix1: Int, ix2: Int) ext
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override def matchTo(ctx: AssemblyMatchingContext, code: List[(FlowInfo, AssemblyLine)]): Option[List[(FlowInfo, AssemblyLine)]] = {
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val s1s = ctx.get[List[AssemblyLine]](ix1)
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val s2s = ctx.get[List[AssemblyLine]](ix2)
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if (s1s.forall(s1 => s2s.forall(s2 => memoryAccessDoesntOverlap(s1.addrMode, s1.parameter, s2.addrMode, s2.parameter)))) Some(code) else None
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if (s1s.forall(s1 => s2s.forall(s2 => HelperCheckers.memoryAccessDoesntOverlap(s1.addrMode, s1.parameter, s2.addrMode, s2.parameter)))) Some(code) else None
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}
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}
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@ -639,7 +640,7 @@ case class DoesntChangeMemoryAt(addrMode1: Int, param1: Int) extends AssemblyLin
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val a1 = ctx.get[AddrMode.Value](addrMode1)
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val a2 = line.addrMode
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val changesSomeMemory = OpcodeClasses.ChangesMemoryAlways(line.opcode) || line.addrMode != AddrMode.Implied && OpcodeClasses.ChangesMemoryIfNotImplied(line.opcode)
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!changesSomeMemory || memoryAccessDoesntOverlap(a1, p1, a2, p2)
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!changesSomeMemory || HelperCheckers.memoryAccessDoesntOverlap(a1, p1, a2, p2)
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}
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}
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@ -654,7 +655,7 @@ case class DoesNotConcernMemoryAt(addrMode1: Int, param1: Int) extends AssemblyL
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val p2 = line.parameter
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val a1 = ctx.get[AddrMode.Value](addrMode1)
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val a2 = line.addrMode
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memoryAccessDoesntOverlap(a1, p1, a2, p2)
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HelperCheckers.memoryAccessDoesntOverlap(a1, p1, a2, p2)
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}
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}
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@ -302,4 +302,42 @@ class AssemblyOptimizationSuite extends FunSuite with Matchers {
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""".stripMargin)
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}
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test("Adding a nonet") {
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EmuBenchmarkRun(
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"""
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| word output @$C000
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| byte source @$C002
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| void main () {
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| init()
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| output += source <<<< 1
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| }
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| void init() {
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| output = 0
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| source = $FF
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| }
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""".stripMargin){m =>
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m.readWord(0xc000) should equal(0x1FE)
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}
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}
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test("Common indexing subexpression elimination") {
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EmuBenchmarkRun(
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"""
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| array output [55] @$C000
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| array input = [0,1,2,3,4,5,6,7,8,9,10]
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| void main () {
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| byte indexer
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| indexer = init()
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| output[(indexer + 1) & 7] = input[(indexer + 1) & 7]
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| }
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| byte init() {
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| return 2
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| }
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""".stripMargin){m =>
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m.readWord(0xc003) should equal(3)
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}
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}
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}
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