From dffc6e71d9dbc92cfcd0535db970aa4abd210b1c Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Thu, 5 Jul 2018 00:58:07 +0200 Subject: [PATCH] Optimize operations on known register values --- .../z80/opt/AlwaysGoodZ80Optimizations.scala | 13 ++++++++++--- .../scala/millfork/assembly/z80/opt/CpuStatus.scala | 2 ++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodZ80Optimizations.scala b/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodZ80Optimizations.scala index 01012919..7e2c4a6c 100644 --- a/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodZ80Optimizations.scala +++ b/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodZ80Optimizations.scala @@ -20,7 +20,7 @@ object AlwaysGoodZ80Optimizations { def for6Registers(f: ZRegister.Value => AssemblyRuleSet) = MultipleAssemblyRules( List(ZRegister.B, ZRegister.C, ZRegister.D, ZRegister.E, ZRegister.H, ZRegister.L).map(f)) - val LoadingKnownValueFromAnotherRegister = new RuleBasedAssemblyOptimization("Loading known value from another register", + val UsingKnownValueFromAnotherRegister = new RuleBasedAssemblyOptimization("Using known value from another register", needsFlowInfo = FlowInfoRequirement.ForwardFlow, for7Registers(register => (Elidable & IsRegular8BitLoadFrom(register) & MatchRegister(register, 0)) ~~> ((code, ctx) => @@ -28,7 +28,14 @@ object AlwaysGoodZ80Optimizations { parameter = NumericConstant(ctx.get[Int](0), 1), registers = x.registers.asInstanceOf[TwoRegisters].copy(source = ZRegister.IMM_8) ))) - ) + ), + for6Registers(register => + (Elidable & HasRegisterParam(register) & HasOpcodeIn(Set(AND, ADD, ADC, SUB, SBC, XOR, OR, CP)) & MatchRegister(register, 0)) ~~> ((code, ctx) => + code.map(x => x.copy( + parameter = NumericConstant(ctx.get[Int](0), 1), + registers = OneRegister(ZRegister.IMM_8) + ))) + ), ) val ReloadingKnownValueFromMemory = new RuleBasedAssemblyOptimization("Reloading known value from memory", @@ -180,11 +187,11 @@ object AlwaysGoodZ80Optimizations { val All: List[AssemblyOptimization[ZLine]] = List[AssemblyOptimization[ZLine]]( FreeHL, - LoadingKnownValueFromAnotherRegister, PointlessLoad, ReloadingKnownValueFromMemory, SimplifiableMaths, UnusedLabelRemoval, + UsingKnownValueFromAnotherRegister, ) } diff --git a/src/main/scala/millfork/assembly/z80/opt/CpuStatus.scala b/src/main/scala/millfork/assembly/z80/opt/CpuStatus.scala index 7f1b4b49..421ed19a 100644 --- a/src/main/scala/millfork/assembly/z80/opt/CpuStatus.scala +++ b/src/main/scala/millfork/assembly/z80/opt/CpuStatus.scala @@ -29,6 +29,8 @@ case class CpuStatus(a: Status[Int] = UnknownStatus, hf: Status[Boolean] = UnknownStatus ) { def setRegister(target: ZRegister.Value, value: Status[Int]): CpuStatus = target match { + case ZRegister.IMM_8 => this + case ZRegister.IMM_16 => this case ZRegister.A => this.copy(a = value) case ZRegister.B => this.copy(b = value) case ZRegister.C => this.copy(c = value)