mirror of
https://github.com/KarolS/millfork.git
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More optimizations, including optimizations with jump counting
This commit is contained in:
Karol Stasiak
parent
f5f4c033f3
commit
e28ff16717
@ -4,7 +4,7 @@ import java.nio.charset.StandardCharsets
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import java.nio.file.{Files, Paths}
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import java.util.Locale
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import millfork.assembly.opt.{CmosOptimizations, DangerousOptimizations, SuperOptimizer, UndocumentedOptimizations}
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import millfork.assembly.opt._
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import millfork.buildinfo.BuildInfo
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import millfork.cli.{CliParser, CliStatus}
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import millfork.env.Environment
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@ -87,7 +87,7 @@ object Main {
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env.collectDeclarations(program, options)
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val extras = List(
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if (options.flag(CompilationFlag.EmitIllegals)) UndocumentedOptimizations.All else Nil,
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if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else Nil,
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if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else LaterOptimizations.Nmos,
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if (options.flag(CompilationFlag.DangerousOptimizations)) DangerousOptimizations.All else Nil,
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).flatten
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val goodCycle = List.fill(optLevel - 1)(OptimizationPresets.Good ++ extras).flatten
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@ -107,6 +107,7 @@ object OptimizationPresets {
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LaterOptimizations.UseXInsteadOfStack,
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LaterOptimizations.UseYInsteadOfStack,
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LaterOptimizations.IndexSwitchingOptimization,
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LaterOptimizations.LoadingBranchesOptimization,
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)
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val Good: List[AssemblyOptimization] = List[AssemblyOptimization](
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@ -114,6 +115,7 @@ object OptimizationPresets {
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AlwaysGoodOptimizations.CarryFlagConversion,
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DangerousOptimizations.ConstantIndexOffsetPropagation,
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AlwaysGoodOptimizations.BranchInPlaceRemoval,
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AlwaysGoodOptimizations.CommonBranchBodyOptimization,
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AlwaysGoodOptimizations.ConstantFlowAnalysis,
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AlwaysGoodOptimizations.ConstantIndexPropagation,
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AlwaysGoodOptimizations.FlagFlowAnalysis,
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@ -146,5 +148,6 @@ object OptimizationPresets {
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UnusedLabelRemoval,
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AlwaysGoodOptimizations.TailCallOptimization,
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AlwaysGoodOptimizations.UnusedCodeRemoval,
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AlwaysGoodOptimizations.UnusedLabelRemoval,
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)
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}
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@ -137,7 +137,8 @@ object OpcodeClasses {
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val SupportsZeroPageIndirect = Set(ORA, AND, EOR, ADC, STA, LDA, CMP, SBC)
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val ShortBranching = Set(BEQ, BNE, BMI, BPL, BVC, BVS, BCC, BCS, BRA)
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val ShortConditionalBranching = Set(BEQ, BNE, BMI, BPL, BVC, BVS, BCC, BCS)
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val ShortBranching = ShortConditionalBranching + BRA
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val AllDirectJumps = ShortBranching + JMP
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val AllLinear = Set(
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ORA, AND, EOR,
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@ -14,7 +14,7 @@ case object EmptyChunk extends Chunk {
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}
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case class LabelledChunk(label: String, chunk: Chunk) extends Chunk {
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override def linearize: List[AssemblyLine] = AssemblyLine.label(Label(label)) :: chunk.linearize
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override def linearize: List[AssemblyLine] = AssemblyLine.label(Label(label)).copy(elidable=false) :: chunk.linearize
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override def sizeInBytes: Int = chunk.sizeInBytes
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}
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@ -846,5 +846,22 @@ object AlwaysGoodOptimizations {
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Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0)-1)) ~~> (_ => List(AssemblyLine.implied(DEX))),
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)
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val CommonBranchBodyOptimization = new RuleBasedAssemblyOptimization("Common branch body optimization",
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needsFlowInfo = FlowInfoRequirement.JustLabels,
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(Elidable & Linear & MatchOpcode(3) & MatchAddrMode(4) & MatchParameter(5)).capture(1) ~
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(
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(HasOpcode(JMP) & MatchParameter(2)) ~ Not(MatchOpcode(3)).*
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).capture(11) ~
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(Elidable & Linear & MatchOpcode(3) & MatchAddrMode(4) & MatchParameter(5)) ~
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)).capture(12) ~~> { (code, ctx) =>
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ctx.get[List[AssemblyLine]](11) ++ ctx.get[List[AssemblyLine]](12) :+ code.head
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}
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)
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val UnusedLabelRemoval = new RuleBasedAssemblyOptimization("Unused label removal",
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needsFlowInfo = FlowInfoRequirement.JustLabels,
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(Elidable & HasOpcode(LABEL) & HasCallerCount(0)) ~~> (_ => Nil)
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)
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}
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@ -1,34 +1,53 @@
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package millfork.assembly.opt
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import millfork.{CompilationFlag, CompilationOptions}
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import millfork.assembly.{AssemblyLine, State}
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import millfork.env.NormalFunction
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import millfork.assembly.{AssemblyLine, Opcode, State}
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import millfork.env.{Label, MemoryAddressConstant, NormalFunction}
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/**
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* @author Karol Stasiak
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*/
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case class FlowInfo(statusBefore: CpuStatus, importanceAfter: CpuImportance) {
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case class FlowInfo(statusBefore: CpuStatus, importanceAfter: CpuImportance, labelUseCountMap: Option[Map[String, Int]]) {
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def hasClear(state: State.Value): Boolean = statusBefore.hasClear(state)
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def hasSet(state: State.Value): Boolean = statusBefore.hasSet(state)
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def isUnimportant(state: State.Value): Boolean = importanceAfter.isUnimportant(state)
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def labelUseCount(label: String): Int = labelUseCountMap.map(_.getOrElse(label, 0)).getOrElse(-1)
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}
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object FlowInfo {
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val Default = FlowInfo(CpuStatus(), CpuImportance())
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val Default = FlowInfo(CpuStatus(), CpuImportance(), None)
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}
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object FlowAnalyzer {
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def analyze(f: NormalFunction, code: List[AssemblyLine], options: CompilationOptions): List[(FlowInfo, AssemblyLine)] = {
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val forwardFlow = if (options.flag(CompilationFlag.DetailedFlowAnalysis)) {
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QuantumFlowAnalyzer.analyze(f, code).map(_.collapse)
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} else {
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CoarseFlowAnalyzer.analyze(f, code)
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def analyze(f: NormalFunction, code: List[AssemblyLine], options: CompilationOptions, req: FlowInfoRequirement.Value): List[(FlowInfo, AssemblyLine)] = {
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val forwardFlow = req match {
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case FlowInfoRequirement.BothFlows | FlowInfoRequirement.ForwardFlow =>
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if (options.flag(CompilationFlag.DetailedFlowAnalysis)) {
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QuantumFlowAnalyzer.analyze(f, code).map(_.collapse)
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} else {
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CoarseFlowAnalyzer.analyze(f, code)
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}
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case FlowInfoRequirement.BackwardFlow | FlowInfoRequirement.JustLabels | FlowInfoRequirement.NoRequirement =>
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List.fill(code.size)(CpuStatus())
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}
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val reverseFlow = ReverseFlowAnalyzer.analyze(f, code)
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forwardFlow.zip(reverseFlow).map{case (s,i) => FlowInfo(s,i)}.zip(code)
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val reverseFlow = req match {
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case FlowInfoRequirement.BothFlows | FlowInfoRequirement.BackwardFlow =>
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ReverseFlowAnalyzer.analyze(f, code)
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case FlowInfoRequirement.ForwardFlow | FlowInfoRequirement.JustLabels | FlowInfoRequirement.NoRequirement =>
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List.fill(code.size)(CpuImportance())
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}
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val labelMap = req match {
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case FlowInfoRequirement.NoRequirement => None
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case _ => Some(code.flatMap {
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case AssemblyLine(op, _, MemoryAddressConstant(Label(l)), _) if op != Opcode.LABEL => Some(l)
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case _ => None
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}.groupBy(identity).mapValues(_.size))
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}
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forwardFlow.zip(reverseFlow).map { case (s, i) => FlowInfo(s, i, labelMap) }.zip(code)
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}
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}
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@ -1,6 +1,6 @@
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package millfork.assembly.opt
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import millfork.assembly.{AddrMode, AssemblyLine, Opcode, State}
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import millfork.assembly._
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import millfork.assembly.Opcode._
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import millfork.assembly.AddrMode._
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import millfork.assembly.OpcodeClasses._
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@ -228,15 +228,140 @@ object LaterOptimizations {
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)
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private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY)
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private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX)
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private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY)
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private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX)
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private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage)
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private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = {
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val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes
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val stAddrModes = if (useX) StxAddrModes else StyAddrModes
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val ldOp = if (useX) LDX else LDY
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val stOp = if (useX) STX else STY
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val changeOp = if (dec) if (useX) DEX else DEY else if (useX) INX else INY
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val addOp = if (dec) SBC else ADC
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val addParam = if (dec ^ carrySet) amount + 1 else amount
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val indexState = if (useX) State.X else State.Y
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val cState = if (carrySet) HasSet(State.C) else HasClear(State.C)
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val carryOp = if (carrySet) SEC else CLC
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes)).capture(11) ~
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(Elidable & HasOpcode(carryOp)).? ~
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(Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState & HasClear(State.D)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) ::
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(List.fill(amount)(AssemblyLine.implied(changeOp)) :+
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ctx.get[List[AssemblyLine]](12).head.copy(opcode = stOp))
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}
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}
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val IncrementThroughIndexRegisters = new RuleBasedAssemblyOptimization("Increment through index registers",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = false),
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)
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val LoadingBranchesOptimization = new RuleBasedAssemblyOptimization("Loading branches optimization",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes) & DoesntMatterWhatItDoesWith(State.X)) ~
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(Linear & Not(ConcernsX) & Not(ChangesA) & Not(HasOpcode(CMP)) & (Not(ReadsA) | Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes)) ).*.capture(39) ~
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(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)).?.capture(40) ~
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(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
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(Elidable & HasOpcode(LDA)).capture(31) ~
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(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
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(Elidable & HasOpcode(LDA)).capture(32) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1) & DoesntMatterWhatItDoesWith(State.A, State.X, State.N, State.Z)) ~~> { (code, ctx) =>
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val ldx = List(code.head.copy(opcode = LDX))
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val stx = ctx.get[List[AssemblyLine]](39).map(l => if (l.opcode == STA) l.copy(opcode = STX) else l )
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val cpx = ctx.get[List[AssemblyLine]](40).map(_.copy(opcode = CPX))
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val branch = ctx.get[List[AssemblyLine]](41)
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val label = ctx.get[List[AssemblyLine]](42)
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val loadIfJumped = ctx.get[List[AssemblyLine]](32)
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val loadIfNotJumped = ctx.get[List[AssemblyLine]](31)
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List(loadIfJumped, ldx, stx, cpx, branch, loadIfNotJumped, label).flatten
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},
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes) & DoesntMatterWhatItDoesWith(State.Y)) ~
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(Linear & Not(ConcernsY) & Not(ChangesA) & Not(HasOpcode(CMP)) & (Not(ReadsA) | Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes)) ).*.capture(39) ~
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(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)).?.capture(40) ~
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(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
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(Elidable & HasOpcode(LDA)).capture(31) ~
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(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
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(Elidable & HasOpcode(LDA)).capture(32) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1) & DoesntMatterWhatItDoesWith(State.A, State.Y, State.N, State.Z)) ~~> { (code, ctx) =>
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val ldy = List(code.head.copy(opcode = LDY))
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val sty = ctx.get[List[AssemblyLine]](39).map(l => if (l.opcode == STA) l.copy(opcode = STY) else l )
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val cpy = ctx.get[List[AssemblyLine]](40).map(_.copy(opcode = CPY))
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val branch = ctx.get[List[AssemblyLine]](41)
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val label = ctx.get[List[AssemblyLine]](42)
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val loadIfJumped = ctx.get[List[AssemblyLine]](32)
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val loadIfNotJumped = ctx.get[List[AssemblyLine]](31)
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List(loadIfJumped, ldy, sty, cpy, branch, loadIfNotJumped, label).flatten
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},
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(HasOpcode(LDA) & DoesntMatterWhatItDoesWith(State.X)) ~
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(Linear & Not(ConcernsX)).*.capture(39) ~
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(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes)).capture(31) ~
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(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes)).capture(32) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.X, State.N, State.Z)).capture(33) ~~> { (code, ctx) =>
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val lda = List(code.head)
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val cmp = ctx.get[List[AssemblyLine]](39)
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val branch = ctx.get[List[AssemblyLine]](41)
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val label = ctx.get[List[AssemblyLine]](42)
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val loadIfJumped = ctx.get[List[AssemblyLine]](32).map(_.copy(opcode = LDX))
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val loadIfNotJumped = ctx.get[List[AssemblyLine]](31).map(_.copy(opcode = LDX))
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val stx = ctx.get[List[AssemblyLine]](33).map(_.copy(opcode = STX))
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List(loadIfJumped, lda, cmp, branch, loadIfNotJumped, label, stx).flatten
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},
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(HasOpcode(LDA) & DoesntMatterWhatItDoesWith(State.Y)) ~
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(Linear & Not(ConcernsY)).*.capture(39) ~
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(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes)).capture(31) ~
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(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes)).capture(32) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.Y, State.N, State.Z)).capture(33) ~~> { (code, ctx) =>
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val lda = List(code.head)
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val cmp = ctx.get[List[AssemblyLine]](39)
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val branch = ctx.get[List[AssemblyLine]](41)
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val label = ctx.get[List[AssemblyLine]](42)
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val loadIfJumped = ctx.get[List[AssemblyLine]](32).map(_.copy(opcode = LDY))
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val loadIfNotJumped = ctx.get[List[AssemblyLine]](31).map(_.copy(opcode = LDY))
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val sty = ctx.get[List[AssemblyLine]](33).map(_.copy(opcode = STY))
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List(loadIfJumped, lda, cmp, branch, loadIfNotJumped, label, sty).flatten
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},
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)
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val All = List(
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DoubleLoadToDifferentRegisters,
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DoubleLoadToTheSameRegister,
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IndexSwitchingOptimization,
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LoadingBranchesOptimization,
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PointlessLoadAfterStore,
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PointessLoadingForShifting,
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LoadingAfterShifting,
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UseXInsteadOfStack,
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UseYInsteadOfStack,
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UseZeropageAddressingMode)
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val Nmos = List(
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IncrementThroughIndexRegisters
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)
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}
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@ -13,16 +13,16 @@ import scala.collection.mutable
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object FlowInfoRequirement extends Enumeration {
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val NoRequirement, BothFlows, ForwardFlow, BackwardFlow = Value
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val NoRequirement, JustLabels, BothFlows, ForwardFlow, BackwardFlow = Value
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def assertForward(x: FlowInfoRequirement.Value): Unit = x match {
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case BothFlows | ForwardFlow => ()
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case NoRequirement | BackwardFlow => ErrorReporting.fatal("Forward flow info required")
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case NoRequirement | JustLabels | BackwardFlow => ErrorReporting.fatal("Forward flow info required")
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}
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def assertBackward(x: FlowInfoRequirement.Value): Unit = x match {
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case BothFlows | BackwardFlow => ()
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case NoRequirement | ForwardFlow => ErrorReporting.fatal("Backward flow info required")
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case NoRequirement | JustLabels | ForwardFlow => ErrorReporting.fatal("Backward flow info required")
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}
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}
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@ -32,18 +32,7 @@ class RuleBasedAssemblyOptimization(val name: String, val needsFlowInfo: FlowInf
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override def optimize(f: NormalFunction, code: List[AssemblyLine], options: CompilationOptions): List[AssemblyLine] = {
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val effectiveCode = code.map(a => a.copy(parameter = a.parameter.quickSimplify))
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val taggedCode = needsFlowInfo match {
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case FlowInfoRequirement.NoRequirement => effectiveCode.map(FlowInfo.Default -> _)
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case FlowInfoRequirement.BothFlows => FlowAnalyzer.analyze(f, effectiveCode, options)
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case FlowInfoRequirement.ForwardFlow =>
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if (options.flag(CompilationFlag.DetailedFlowAnalysis)) {
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QuantumFlowAnalyzer.analyze(f, code).map(s => FlowInfo(s.collapse, CpuImportance())).zip(code)
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} else {
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CoarseFlowAnalyzer.analyze(f, code).map(s => FlowInfo(s, CpuImportance())).zip(code)
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}
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case FlowInfoRequirement.BackwardFlow =>
|
||||
ReverseFlowAnalyzer.analyze(f, code).map(i => FlowInfo(CpuStatus(), i)).zip(code)
|
||||
}
|
||||
val taggedCode = FlowAnalyzer.analyze(f, effectiveCode, options, needsFlowInfo)
|
||||
optimizeImpl(f, taggedCode, options)
|
||||
}
|
||||
|
||||
@ -754,4 +743,12 @@ case class Before(pattern: AssemblyPattern) extends AssemblyLinePattern {
|
||||
}
|
||||
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean = ???
|
||||
}
|
||||
|
||||
case class HasCallerCount(count: Int) extends AssemblyLinePattern {
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean =
|
||||
line match {
|
||||
case AssemblyLine(Opcode.LABEL, _, MemoryAddressConstant(Label(l)), _) => flowInfo.labelUseCount(l) == count
|
||||
case _ => false
|
||||
}
|
||||
}
|
||||
@ -21,6 +21,8 @@ object SuperOptimizer extends AssemblyOptimization {
|
||||
}
|
||||
if (options.flag(CompilationFlag.EmitCmosOpcodes)) {
|
||||
allOptimizers ++= CmosOptimizations.All
|
||||
} else {
|
||||
allOptimizers ++= LaterOptimizations.Nmos
|
||||
}
|
||||
allOptimizers ++= List(
|
||||
VariableToRegisterOptimization,
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
package millfork.test
|
||||
|
||||
import millfork.test.emu.EmuBenchmarkRun
|
||||
import millfork.test.emu.{EmuBenchmarkRun, EmuSuperOptimizedRun, EmuUltraBenchmarkRun}
|
||||
import org.scalatest.{FunSuite, Matchers}
|
||||
|
||||
/**
|
||||
@ -55,7 +55,7 @@ class ComparisonSuite extends FunSuite with Matchers {
|
||||
}
|
||||
|
||||
test("Carry flag optimization test") {
|
||||
EmuBenchmarkRun(
|
||||
EmuUltraBenchmarkRun(
|
||||
"""
|
||||
| byte output @$c000
|
||||
| void main () {
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.opt.LaterOptimizations
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
/**
|
||||
@ -8,7 +9,10 @@ import millfork.{Cpu, OptimizationPresets}
|
||||
object EmuOptimizedInlinedRun extends EmuRun(
|
||||
Cpu.StrictMos,
|
||||
OptimizationPresets.NodeOpt,
|
||||
OptimizationPresets.AssOpt ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ OptimizationPresets.Good,
|
||||
OptimizationPresets.AssOpt ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good,
|
||||
false)
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.opt.LaterOptimizations
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
/**
|
||||
@ -8,7 +9,10 @@ import millfork.{Cpu, OptimizationPresets}
|
||||
object EmuOptimizedRun extends EmuRun(
|
||||
Cpu.StrictMos,
|
||||
OptimizationPresets.NodeOpt,
|
||||
OptimizationPresets.AssOpt ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ OptimizationPresets.Good,
|
||||
OptimizationPresets.AssOpt ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good,
|
||||
false)
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.opt.LaterOptimizations
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
/**
|
||||
@ -8,7 +9,10 @@ import millfork.{Cpu, OptimizationPresets}
|
||||
object EmuQuantumOptimizedRun extends EmuRun(
|
||||
Cpu.StrictMos,
|
||||
OptimizationPresets.NodeOpt,
|
||||
OptimizationPresets.AssOpt ++ OptimizationPresets.Good ++ OptimizationPresets.Good ++ OptimizationPresets.Good,
|
||||
OptimizationPresets.AssOpt ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good,
|
||||
true)
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.opt.UndocumentedOptimizations
|
||||
import millfork.assembly.opt.{LaterOptimizations, UndocumentedOptimizations}
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
/**
|
||||
@ -9,7 +9,11 @@ import millfork.{Cpu, OptimizationPresets}
|
||||
object EmuUndocumentedRun extends EmuRun(
|
||||
Cpu.Ricoh, // not Cpu.Mos, because I haven't found an emulator that supports both illegals and decimal mode yet
|
||||
OptimizationPresets.NodeOpt,
|
||||
OptimizationPresets.AssOpt ++ UndocumentedOptimizations.All ++ OptimizationPresets.Good ++ UndocumentedOptimizations.All ++ OptimizationPresets.Good,
|
||||
OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.Good,
|
||||
false) {
|
||||
|
||||
override def emitIllegals = true
|
||||
|
||||
Loading…
Reference in New Issue
Block a user