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Fix init_rw_memory
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c1224f0795
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@ -77,13 +77,13 @@ __init_rw_memory__skip3:
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#pragma zilog_syntax
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noinline asm void init_rw_memory() {
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ld bc,__rwdata_size
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ld a,b
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or c
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ret z
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+ memory_barrier()
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ld hl,__rwdata_init_start
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ld de,__rwdata_start
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ld bc,__rwdata_size
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ldir
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+ memory_barrier()
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ret
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@ -93,11 +93,11 @@ noinline asm void init_rw_memory() {
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#pragma zilog_syntax
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noinline asm void init_rw_memory() {
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ld bc,__rwdata_size
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ld a,b
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or c
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ret z
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+ memory_barrier()
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ld bc,__rwdata_size
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ld hl,__rwdata_init_start
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ld de,__rwdata_start
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__init_rw_memory__loop1:
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@ -111,6 +111,28 @@ __init_rw_memory__loop1:
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ret
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}
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#elseif ARCH_6809
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noinline asm void init_rw_memory() {
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// TODO: optimal register allocation
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ldd __rwdata_size
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beq __init_rw_memory_end
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+ memory_barrier()
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pshs u
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ldx __rwdata_init_start
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ldu __rwdata_start
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__init_rw_memory__loop1:
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ldb ,x
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stb ,u
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leax 1,x
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cmpx #__rwdata_init_start+__rwdata_size
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? bne __init_rw_memory__loop1
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+ memory_barrier()
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puls u
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__init_rw_memory_end:
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rts
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}
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#else
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#error Unsupported architecture for init_rw_memory
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