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Z80: Fix stack variable inlining

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This commit is contained in:
Karol Stasiak 2019-06-23 22:31:46 +02:00
parent 63c43c414a
commit f22b62e57f
1 changed files with 4 additions and 0 deletions
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4
src/main/scala/millfork/assembly/z80/opt/ByteVariableToRegisterOptimization.scala
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@ -337,6 +337,8 @@ object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
case ZLine(LD, TwoRegistersOffset(reg, MEM_IX_D, off), _, _, s) :: xs if "IX+" + off == vname =>
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
else ZLine.ld8(reg, target).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
case ZLine(LD, TwoRegistersOffset(MEM_IX_D, IMM_8, off), param, _, s) :: xs if "IX+" + off == vname =>
ZLine.ldImm8(target, param).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
case ZLine(LD, TwoRegistersOffset(MEM_IX_D, reg, off), _, _, s) :: xs if "IX+" + off == vname =>
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
else ZLine.ld8(target, reg).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
@ -346,6 +348,8 @@ object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
case ZLine(LD, TwoRegistersOffset(reg, MEM_IY_D, off), _, _, s) :: xs if "IY+" + off == vname =>
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
else ZLine.ld8(reg, target).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
case ZLine(LD, TwoRegistersOffset(MEM_IY_D, IMM_8, off), param, _, s) :: xs if "IY+" + off == vname =>
ZLine.ldImm8(target, param).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
case ZLine(LD, TwoRegistersOffset(MEM_IY_D, reg, off), _, _, s) :: xs if "IY+" + off == vname =>
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
else ZLine.ld8(target, reg).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)