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8080: Fix word negation

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This commit is contained in:
Karol Stasiak 2020-11-11 00:25:39 +01:00
parent f39810793b
commit f4a3601d6e
2 changed files with 29 additions and 1 deletions
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16
src/main/scala/millfork/compiler/z80/ZBuiltIns.scala
View File

@ -279,7 +279,21 @@ object ZBuiltIns {
ctx.env.eval(expr) match {
case None =>
if (result.isEmpty) {
???
if (ctx.options.flag(CompilationFlag.EmitZ80Opcodes)) {
result ++= Z80ExpressionCompiler.compileToBC(ctx, expr)
result += ZLine.ldImm16(ZRegister.HL, 0)
result += ZLine.register(OR, ZRegister.A)
result += ZLine.registers(SBC_16, ZRegister.HL, ZRegister.BC)
} else {
result ++= Z80ExpressionCompiler.compileToHL(ctx, expr)
result += ZLine.register(DEC_16, ZRegister.HL)
result += ZLine.ld8(ZRegister.A, ZRegister.H)
result += ZLine.implied(CPL)
result += ZLine.ld8(ZRegister.H, ZRegister.A)
result += ZLine.ld8(ZRegister.A, ZRegister.L)
result += ZLine.implied(CPL)
result += ZLine.ld8(ZRegister.L, ZRegister.A)
}
} else {
if (ctx.options.flag(CompilationFlag.EmitZ80Opcodes)) {
// TODO: optimize

14
src/test/scala/millfork/test/WordMathSuite.scala
View File

@ -268,6 +268,20 @@ class WordMathSuite extends FunSuite with Matchers with AppendedClues {
}
}
test("Word addition 6") {
EmuCrossPlatformBenchmarkRun(Cpu.Sixteen, Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Intel8085, Cpu.Sharp, Cpu.Intel8086, Cpu.Motorola6809)("""
| byte output @$c000
| void main () {
| signed16 p
| p = f()
| output = lo(-p)
| }
| noinline signed16 f() = 6
""".stripMargin) { m =>
m.readByte(0xc000) should equal((-6) & 0xff)
}
}
test("Word bit ops 2") {
EmuCrossPlatformBenchmarkRun(Cpu.Sixteen, Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Sharp, Cpu.Intel8086, Cpu.Motorola6809)("""
| word output @$c000