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8080: Fixed inlining of byte-sized variables into registers
This commit is contained in:
Karol Stasiak
parent
2ad43cf3b3
commit
f90d6afc43
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@ -74,6 +74,8 @@
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* Fixed for-each loops with non-constant arrays.
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* 8080 and LR35902: Fixed inlining of byte-sized variables into registers.
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* 8080 and LR35902: fixed large stack variables.
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* Other bug fixes.
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@ -270,6 +270,25 @@ object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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if (target == D || target == E) fail(61) else
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(10, 3)))
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// TODO: other combinations:
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case (_, ZLine0(LD, TwoRegisters(L, C), _)) :: (_, ZLine0(LD, TwoRegisters(H, B), _)) :: xs if addressInBc.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(H, B), _)) :: (_, ZLine0(LD, TwoRegisters(L, C), _)) :: xs if addressInBc.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(L, E), _)) :: (_, ZLine0(LD, TwoRegisters(H, D), _)) :: xs if addressInDe.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(H, D), _)) :: (_, ZLine0(LD, TwoRegisters(L, E), _)) :: xs if addressInDe.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(C, L), _)) :: (_, ZLine0(LD, TwoRegisters(B, H), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(true), addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(B, H), _)) :: (_, ZLine0(LD, TwoRegisters(C, L), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(true), addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(E, L), _)) :: (_, ZLine0(LD, TwoRegisters(D, H), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(D, H), _)) :: (_, ZLine0(LD, TwoRegisters(E, L), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(_, OneRegister(MEM_HL), _)) :: xs => addressInHl match {
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case Some(true) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(3, 0)))
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case Some(false) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
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@ -388,15 +407,34 @@ object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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x.copy(registers = TwoRegisters(reg, target), parameter = p) ::
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inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
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// TODO: other combinations
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case ZLine0(LD, TwoRegisters(L, C), _) :: ZLine0(LD, TwoRegisters(H, B), _) :: xs if addressInBc =>
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inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
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case ZLine0(LD, TwoRegisters(H, B), _) :: ZLine0(LD, TwoRegisters(L, C), _) :: xs if addressInBc =>
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inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
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case ZLine0(LD, TwoRegisters(L, E), _) :: ZLine0(LD, TwoRegisters(H, D), _) :: xs if addressInDe =>
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inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
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case ZLine0(LD, TwoRegisters(H, D), _) :: ZLine0(LD, TwoRegisters(L, E), _) :: xs if addressInDe =>
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inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
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case ZLine0(LD, TwoRegisters(C, L), _) :: ZLine0(LD, TwoRegisters(B, H), _) :: xs if addressInHl =>
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inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
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case ZLine0(LD, TwoRegisters(B, H), _) :: ZLine0(LD, TwoRegisters(C, L), _) :: xs if addressInHl =>
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inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
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case ZLine0(LD, TwoRegisters(E, L), _) :: ZLine0(LD, TwoRegisters(D, H), _) :: xs if addressInHl =>
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inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
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case ZLine0(LD, TwoRegisters(D, H), _) :: ZLine0(LD, TwoRegisters(E, L), _) :: xs if addressInHl =>
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inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
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case (x@ZLine(CALL,_,_,_,s))::xs =>
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// TODO: this push/pull pair shouldn't prevent the inlining to the other register in the pair
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target match {
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case ZRegister.B | ZRegister.C =>
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ZLine.register(PUSH, BC).pos(s) :: x :: ZLine.register(POP, BC).pos(s) ::
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inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
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inlineVars(vname, target, addressInHl = false, addressInBc, addressInDe = false, xs)
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case ZRegister.D | ZRegister.E =>
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ZLine.register(PUSH, DE).pos(s) :: x :: ZLine.register(POP, DE).pos(s) ::
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inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
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inlineVars(vname, target, addressInHl = false, addressInBc = false, addressInDe, xs)
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}
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case x :: xs if x.changesRegister(HL) =>
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@ -1,7 +1,7 @@
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package millfork.assembly.z80.opt
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import millfork.assembly.opt.SingleStatus
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import millfork.assembly.z80.{OneRegister, TwoRegisters, ZLine, ZLine0}
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import millfork.assembly.z80.{OneRegister, TwoRegisters, ZLine, ZLine0, ZOpcode}
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import millfork.env._
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import millfork.error.ConsoleLogger
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import millfork.node.ZRegister
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@ -14,17 +14,38 @@ object VariableLifetime {
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// This only works for non-stack variables.
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// TODO: this is also probably very wrong
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def apply(variableName: String, codeWithFlow: List[(FlowInfo, ZLine)]): Range = {
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import ZRegister._
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import ZOpcode._
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val pointerLoadedAt = codeWithFlow.zipWithIndex.filter{
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case ((_, ZLine0(ZOpcode.LD_16, TwoRegisters(_, IMM_16), MemoryAddressConstant(MemoryVariable(n, _, _)))), _) => n == variableName
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case _ => false
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}.map(_._2)
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val pointerReadAt = codeWithFlow.zipWithIndex.filter{
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case ((_, ZLine0(_, TwoRegisters(MEM_HL | MEM_DE | MEM_BC, _), _)), _) => true
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case ((_, ZLine0(_, TwoRegisters(_, MEM_HL | MEM_DE | MEM_BC), _)), _) => true
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case ((_, ZLine0(_, OneRegister(MEM_HL | MEM_DE | MEM_BC), _)), _) => true
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case ((_, ZLine0(CALL, _, _)), _) => true
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case _ => false
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}.map(_._2)
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val flags = codeWithFlow.map {
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case (_, ZLine0(_, _, MemoryAddressConstant(MemoryVariable(n, _, _)))) => n == variableName
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case (_, ZLine0(_, _, CompoundConstant(MathOperator.Plus, MemoryAddressConstant(MemoryVariable(n, _, _)), NumericConstant(_, 1)))) => n == variableName
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case (i, ZLine0(_, TwoRegisters(ZRegister.MEM_HL, _) | TwoRegisters(_, ZRegister.MEM_HL) | OneRegister(ZRegister.MEM_HL), _)) =>
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case (i, ZLine0(_, TwoRegisters(MEM_HL, _) | TwoRegisters(_, MEM_HL) | OneRegister(MEM_HL), _)) =>
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i.statusBefore.hl match {
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case SingleStatus(MemoryAddressConstant(MemoryVariable(n, _, _))) => n == variableName
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case SingleStatus(CompoundConstant(MathOperator.Plus, MemoryAddressConstant(MemoryVariable(n, _, _)), NumericConstant(_, 1))) => n == variableName
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case _ => false
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}
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case _ => false
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}.toArray
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if(pointerLoadedAt.nonEmpty) {
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pointerReadAt.foreach(i => flags(i) = true)
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}
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if (flags.forall(!_)) return Range(0, 0)
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var min = flags.indexOf(true)
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var max = flags.lastIndexOf(true) + 1
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