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Flow analysis fixes
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8cc3399239
commit
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@ -10,21 +10,27 @@ import millfork.env.{Label, MemoryAddressConstant, NormalFunction, NumericConsta
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object CoarseFlowAnalyzer {
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object CoarseFlowAnalyzer {
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def analyze(f: NormalFunction, code: List[AssemblyLine], compilationOptions: CompilationOptions): List[CpuStatus] = {
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def analyze(f: NormalFunction, code: List[AssemblyLine], compilationOptions: CompilationOptions): List[CpuStatus] = {
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val emptyIz: Status[Int] = if (compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)) UnknownStatus else SingleStatus(0)
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val ceFlag = compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)
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val emptyStatus = CpuStatus(iz = emptyIz)
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val cmosFlag = compilationOptions.flag(CompilationFlag.EmitCmosOpcodes)
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val initialStatus =
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if (compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)) CpuStatus.initialStatusCE
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else CpuStatus.initialStatusStandard
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val functionStartStatus =
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if (f.interrupt) {
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if (ceFlag) CpuStatus.initialInterruptStatusCE
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else if (cmosFlag) CpuStatus.initialInterruptStatusCE
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else CpuStatus.initialInterruptStatusStandard
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} else initialStatus
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val emptyStatus =
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if (compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)) CpuStatus.emptyStatusCE
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else CpuStatus.emptyStatusStandard
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val flagArray = Array.fill[CpuStatus](code.length)(emptyStatus)
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val flagArray = Array.fill[CpuStatus](code.length)(emptyStatus)
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val codeArray = code.toArray
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val codeArray = code.toArray
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val initialStatus = CpuStatus(
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = emptyIz
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)
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var changed = true
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var changed = true
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while (changed) {
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while (changed) {
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changed = false
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changed = false
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var currentStatus: CpuStatus = if (f.interrupt) emptyStatus else initialStatus
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var currentStatus: CpuStatus = functionStartStatus
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for (i <- codeArray.indices) {
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for (i <- codeArray.indices) {
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import millfork.assembly.Opcode._
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import millfork.assembly.Opcode._
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import millfork.assembly.AddrMode._
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import millfork.assembly.AddrMode._
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@ -38,7 +44,7 @@ object CoarseFlowAnalyzer {
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currentStatus = codeArray.indices.flatMap(j => codeArray(j) match {
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currentStatus = codeArray.indices.flatMap(j => codeArray(j) match {
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case AssemblyLine(_, _, MemoryAddressConstant(Label(L)), _) => Some(flagArray(j))
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case AssemblyLine(_, _, MemoryAddressConstant(Label(L)), _) => Some(flagArray(j))
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case _ => None
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case _ => None
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}).fold(emptyStatus)(_ ~ _)
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}).fold(currentStatus)(_ ~ _)
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case AssemblyLine(JSR | BYTE, _, _, _) =>
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case AssemblyLine(JSR | BYTE, _, _, _) =>
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currentStatus = initialStatus
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currentStatus = initialStatus
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@ -364,3 +364,76 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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case _ => false
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case _ => false
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}
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}
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}
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}
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object CpuStatus {
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val initialStatusStandard = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = SingleStatus(0)
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)
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val initialStatusCE = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = AnyStatus
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)
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val initialInterruptStatusStandard = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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d = AnyStatus,
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0)
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)
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val initialInterruptStatusCmos = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0)
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)
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val initialInterruptStatusCE = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = AnyStatus
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)
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val emptyStatusStandard = CpuStatus(iz = SingleStatus(0))
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val emptyStatusCE = CpuStatus(iz = AnyStatus)
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}
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@ -262,7 +262,7 @@ object FlowAnalyzerForTheRest {
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CPX -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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CPX -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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CPY -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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CPY -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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CPZ -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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CPZ -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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BIT -> (_.copy(c = AnyStatus, v = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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BIT -> (_.copy(v = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
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TRB -> (_.copy(z = AnyStatus, src = AnyStatus)),
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TRB -> (_.copy(z = AnyStatus, src = AnyStatus)),
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TSB -> (_.copy(z = AnyStatus, src = AnyStatus)),
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TSB -> (_.copy(z = AnyStatus, src = AnyStatus)),
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JMP -> (_ => CpuStatus()),
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JMP -> (_ => CpuStatus()),
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@ -150,6 +150,14 @@ object ReverseFlowAnalyzerPerOpcode {
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n = Unimportant, z = Unimportant,
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n = Unimportant, z = Unimportant,
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m = Important)
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m = Important)
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}),
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}),
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BIT -> (currentImportance => {
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currentImportance.copy(
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a = currentImportance.z,
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n = Unimportant,
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z = Unimportant,
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v = Unimportant,
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m = Important)
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}),
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ADC -> (currentImportance => {
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ADC -> (currentImportance => {
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val ignoreOutput = allAddingOutputsUnimportant(currentImportance)
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val ignoreOutput = allAddingOutputsUnimportant(currentImportance)
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