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6809: optimize indirect stores

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This commit is contained in:
Karol Stasiak 2020-07-13 23:09:52 +02:00
parent 0b948f801d
commit fff27c59ea
1 changed files with 19 additions and 3 deletions
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22
src/main/scala/millfork/compiler/m6809/M6809ExpressionCompiler.scala
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@ -724,13 +724,22 @@ object M6809ExpressionCompiler extends AbstractExpressionCompiler[MLine] {
val effectiveBase = (p.value + constOffset).quickSimplify val effectiveBase = (p.value + constOffset).quickSimplify
variableIndex match { variableIndex match {
case Some(ix) => case Some(ix) =>
stashIfNeeded(ctx, compileToX(ctx, ix)) :+ MLine.indexedX(store, effectiveBase) compileToX(ctx, ix) match {
case List(MLine0(LDX, Immediate, constAddr)) =>
List(MLine(store, Absolute(false), constAddr + effectiveBase))
case List(MLine0(LDX, Absolute(false), constAddr)) if effectiveBase.isProvablyZero =>
List(MLine(store, Absolute(true), constAddr))
case xs =>
stashIfNeeded(ctx, xs) :+ MLine.indexedX(store, effectiveBase)
}
case None => case None =>
List(MLine.absolute(store, effectiveBase)) List(MLine.absolute(store, effectiveBase))
} }
case v: VariablePointy => case v: VariablePointy =>
ctx.env.eval(index) match { ctx.env.eval(index) match {
case Some(ix) => List(MLine.absolute(LDX, v.addr), MLine.indexedX(store, ix * v.elementType.size)) case Some(ix) =>
if (ix.isProvablyZero) List(MLine(store, Absolute(true), v.addr))
else List(MLine.absolute(LDX, v.addr), MLine.indexedX(store, ix * v.elementType.size))
case _ => case _ =>
v.indexType.size match { v.indexType.size match {
case 1 | 2 => case 1 | 2 =>
@ -759,7 +768,14 @@ object M6809ExpressionCompiler extends AbstractExpressionCompiler[MLine] {
val sl = storeB(ctx, lo) val sl = storeB(ctx, lo)
stashBIfNeeded(ctx, sh) ++ sl // TODO: optimize stashBIfNeeded(ctx, sh) ++ sl // TODO: optimize
case DerefExpression(inner, offset, _) => case DerefExpression(inner, offset, _) =>
stashDIfNeeded(ctx, compileToX(ctx, inner)) :+ MLine(STD, Indexed(M6809Register.X, indirect = false), NumericConstant(offset, 2)) compileToX(ctx, inner) match {
case List(MLine0(LDX, Immediate, constAddr)) =>
List(MLine(STD, Absolute(false), constAddr + offset))
case List(MLine0(LDX, Absolute(false), constAddr)) if offset == 0 =>
List(MLine(STD, Absolute(true), constAddr))
case xs =>
stashDIfNeeded(ctx, xs) :+ MLine(STD, Indexed(M6809Register.X, indirect = false), NumericConstant(offset, 2))
}
} }
} }