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1,316 Commits 1 Branch 18 Tags 5 MiB
1e4a193741
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38 Commits

Author SHA1 Message Date
Karol Stasiak
1e4a193741 Optimization hints 2021-03-15 00:44:14 +01:00
Karol Stasiak
97c7d0ffed Basic groundwork for optimization hint support 2020-11-18 22:37:58 +01:00
Karol Stasiak
b24ac32932 Z80: Support IXH/IXL/IYH/IYL registers. Add Intel syntax for Z80 instructions. 2020-07-24 17:27:37 +02:00
Karol Stasiak
17e660a2f6 Report lines with invalid short branches 2020-03-17 21:46:43 +01:00
Karol Stasiak
83b85ef0fc Support breakpoints in the label file (#44) 2020-03-16 00:01:04 +01:00
Karol Stasiak
d1058b6223 ZX Spectrum Next CPU support 2019-10-01 00:46:15 +02:00
Karol Stasiak
bb63a73f15 Improve interprocedural optimizations 2019-08-01 19:11:35 +02:00
Karol Stasiak
3852b2dbe9 More label file formats 2019-06-14 11:39:11 +02:00
Karol Stasiak
dc13dbaa9a Code cleanup 2019-06-12 22:55:34 +02:00
Karol Stasiak
0f179f79aa Many big important things: 
– Add support for undocumented 8085 instructions
– Convert undocumented  8085 instructions to 8086
– Add new CPU types and categorize CPU types correctly
– Fix macro expansion in some situations
– Improve 8080 optimizations
– Improve documentation
– Other improvements
 2019-06-12 12:06:02 +02:00
Karol Stasiak
b3bb9bb063 Intel 8085 support 2019-05-31 17:27:38 +02:00
Karol Stasiak
b400c884e0 Add memory barriers 2018-12-31 13:20:32 +01:00
Karol Stasiak
badd7ef1d8 Compiler performance improvements 2018-12-16 14:38:57 +01:00
Karol Stasiak
406d69c74a Add original line numbers to generated assembly 2018-12-14 15:42:31 +01:00
Karol Stasiak
9581891d66 Following jumps. Generating conditional returns/calls. 2018-08-08 23:12:20 +02:00
Karol Stasiak
8b09941cef Z80: Jump shortening 2018-08-08 13:45:38 +02:00
Karol Stasiak
ff16854a11 Code deduplication 2018-08-06 19:29:09 +02:00
Karol Stasiak
48b183828b Z80: LDH instruction for LR35902 2018-08-03 16:43:31 +02:00
Karol Stasiak
e952d89849 Z80: Intel syntax for output. 2018-08-01 21:16:20 +02:00
Karol Stasiak
453ce93952 Z80: RLA and RL A are two very different instructions 2018-07-30 23:49:25 +02:00
Karol Stasiak
998902acf6 Refactor: error logging 2018-07-30 18:53:08 +02:00
Karol Stasiak
cb92b09942 Improvements related to large types: 
– returning types larger than 2
– fastcall for 1 parameter of size 3 or 4 on Z80
– more integer types (up to int128)
– marked farword as a deprecated alias of int24
 2018-07-30 14:33:16 +02:00
Karol Stasiak
7ea2fe6a4e Almost full LR35902 opcode space coverage 2018-07-27 19:07:12 +02:00
Karol Stasiak
c5b45947dc Preliminary support for Intel 8080 2018-07-24 23:14:41 +02:00
Karol Stasiak
1e822239d0 Z80: Fix SET n,(IX+d) and related instructions 2018-07-24 20:45:30 +02:00
Karol Stasiak
b724ba9c6a Z80: Full assembly support 2018-07-24 17:40:06 +02:00
Karol Stasiak
e280aca08b Z80: Emit RES and SET instructions 2018-07-24 16:16:49 +02:00
Karol Stasiak
85243c96a7 Z80: The >>>> operator 2018-07-23 13:49:59 +02:00
Karol Stasiak
a39064cf76 Z80: Return dispatch 2018-07-23 13:41:51 +02:00
Karol Stasiak
39dfe13a3f Emit LD (m),BC and similar instructions 2018-07-16 23:01:04 +02:00
Karol Stasiak
215d8d92b4 Preprocessor. Z80 improvements. Library improvements. 2018-07-12 19:39:25 +02:00
Karol Stasiak
a00ba49820 Multiple improvements and fixes: 
– reorganized code for future support of larger zeropage register sets
– added stack-allocated variables for Z80
– added many stack-related optimizations for 6502 and Z80
– fixed flow analysis and optimization bugs for Z80
– flow analysis for stack-allocated variables on Z80
– added more optimizations for 6502 and Z80
– fixed IX/IY-indexed operations on Z80
– code cleanup
 2018-07-06 22:45:59 +02:00
Karol Stasiak
fe85757e00 Initial and very incomplete support for Z80 assembly 2018-07-05 00:49:51 +02:00
Karol Stasiak
57bde60ced Fix Z80 shifting 2018-07-03 01:46:57 +02:00
Karol Stasiak
dc3425f64e Preliminary and partial machine code output for Z80 2018-07-01 22:28:09 +02:00
Karol Stasiak
2500f842e9 Interprocedural optimization plus some minor fixes: 
– fixed handling LDX/LDY/LDZ when inlining variables into registers
– fixed CLA/CLX/CLY instruction generation
– refactored optimization definitions
 2018-06-25 21:29:04 +02:00
Karol Stasiak
daf8461c07 Allocating arbitrary variables in the zeropage and using zeropage addressing when appropriate 2018-06-18 17:59:47 +02:00
Karol Stasiak
0f453e2d2c Start of the Z80 backend 2018-06-17 02:01:35 +02:00