mirror of
https://github.com/KarolS/millfork.git
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1199 lines
62 KiB
Scala
1199 lines
62 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.{CompilationFlag, NonOverlappingIntervals}
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import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext}
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import millfork.assembly.mos._
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import millfork.assembly.mos.Opcode._
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import AddrMode._
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import millfork.env._
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import millfork.error.Logger
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import millfork.node.MosNiceFunctionProperty
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import scala.collection.mutable
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import scala.collection.mutable.ListBuffer
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import scala.util.control.TailCalls.{TailRec, done, tailcall}
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/**
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* @author Karol Stasiak
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*/
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object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine] {
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override def minimumRequiredLines: Int = 2
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override def requiredFlags: Set[CompilationFlag.Value] = Set(CompilationFlag.RegisterVariables)
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object CyclesAndBytes {
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val Zero = CyclesAndBytes(0, 0)
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}
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case class CyclesAndBytes(bytes: Int, cycles: Int) {
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def +(that: CyclesAndBytes) = CyclesAndBytes(this.bytes + that.bytes, this.cycles + that.cycles)
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}
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case class FeaturesForIndexRegisters(
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blastProcessing: Boolean,
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izIsAlwaysZero: Boolean,
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indexRegisterTransfers: Boolean,
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functionsSafeForX: Set[String],
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functionsSafeForY: Set[String],
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functionsSafeForZ: Set[String],
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identityArray: Constant,
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log: Logger)
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case class FeaturesForAccumulator(
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cmos: Boolean,
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safeFunctions: Set[String],
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labelsUsedOnce: Set[String],
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labelsSyncedAt: Set[String],
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log: Logger) {
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override def toString: String = s"{cmos=$cmos, safeFunctions=[${safeFunctions.mkString(",")}], labelsSyncedAt=[${safeFunctions.mkString(",")}]}"
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def addSafeLabel(label: String): FeaturesForAccumulator = copy(labelsSyncedAt = this.labelsSyncedAt + label)
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}
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// If any of these opcodes is present within a method,
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// then it's too hard to assign any variable to a register.
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private val opcodesThatAlwaysPrecludeXAllocation = Set(
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JSR, STX, TXA, INX, DEX, CPX,
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LDX_W, STX_W, CPX_W, DEX_W, INX_W,
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PHX, PLX, PHX_W, PLX_W,
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SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
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HuSAX, SXY, TXY, TXY,
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BYTE,
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)
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private val opcodesThatAlwaysPrecludeYAllocation = Set(
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JSR, STY, TYA, INY, DEY, CPY,
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LDY_W, STY_W, CPY_W, DEY_W, INY_W,
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PHY, PLY, PHY_W, PLY_W,
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AHX, SHX, SHY, LAS, TAS,
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SAY, SXY, TXY, TYX,
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BYTE,
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)
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private val opcodesThatAlwaysPrecludeZAllocation = Set(
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JSR, STZ, TZA, INZ, DEZ, CPZ,
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PHZ, PLZ,
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BYTE,
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)
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private val opcodesThatAlwaysPrecludeAAllocation = Set(
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JSR, PHA, PLA,
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ADC, SBC, ORA, EOR, AND, BIT,
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ADC_W, SBC_W, ORA_W, EOR_W, AND_W, BIT_W,
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RRA, RLA, ISC, SLO, SRE,
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ALR, ARR, ANC, SBX, LXA, XAA,
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AHX, SHX, SHY, LAS, TAS,
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HuSAX, SAY,
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TCD, TDC, TSC, TCS, XBA,
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BYTE,
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)
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private val opcodesThatNeverPrecludeAAllocation = Set(
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INX, INY, DEX, DEY,
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CLC, SEC, CLV, SED, CLD, CLI, SEI, NOP, BRK,
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INX_W, DEX_W, INY_W, DEY_W,
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PHX, PHY, PHZ, PHX_W, PHY_W,
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PLX, PLY, PLZ, PLX_W, PLY_W,
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TXY, TYX, TXS, TSX,
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)
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// If any of these opcodes is used on a variable
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// then it's too hard to assign that variable to a register.
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// Also, LDY prevents assigning a variable to X and LDX and LAX prevent assigning a variable to Y.
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private val opcodesThatCannotBeUsedWithIndexRegistersAsParameters = Set(
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LDX_W, LDY_W, LDA_W,
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BIT, CPX, CPY, STY,
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BIT_W, CPX_W, CPY_W, STY_W,
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EOR, ORA, AND, ADC, SBC, CMP,
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EOR_W, ORA_W, AND_W, ADC_W, SBC_W, CMP_W,
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ROL, ROR, LSR, ASL, STX,
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ROL_W, ROR_W, LSR_W, ASL_W, STX_W,
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INC_W, DEC_W,
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SAX, SLO, SRE, ISC, DCP, RLA, RRA,
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AHX, SHY, SHX, LAS, TAS,
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TRB, TSB,
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ASR,
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)
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private val opcodesThatCannotBeUsedWithAccumulatorAsParameter = Set(
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BIT, CPX, CPY,
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BIT_W, CPX_W, CPY_W,
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EOR, ORA, AND, ADC, SBC, CMP, STA,
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EOR_W, ORA_W, AND_W, ADC_W, SBC_W, CMP_W, STA_W,
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INC_W, DEC_W,
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SAX, SLO, SRE, ISC, DCP, RLA, RRA,
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AHX, SHY, SHX, LAS, TAS,
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TRB, TSB,
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ASR,
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)
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private val opcodesCommutative = Set(AND, ORA, EOR, ADC)
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private val opcodesIdentityTable = Set(AND, ORA, EOR, CMP, ADC, SBC)
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private val LdxAddrModes = Set(ZeroPage, Absolute, Immediate, AbsoluteY, ZeroPageY)
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private val LdyAddrModes = Set(ZeroPage, Absolute, Immediate, AbsoluteX, ZeroPageX)
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private val LdzAddrModes = Set(Absolute, Immediate, AbsoluteX)
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private val CpxyzAddrModes = Set(Absolute, Immediate, ZeroPage)
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override def name = "Allocating variables to index registers"
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override def optimize(f: NormalFunction, code: List[AssemblyLine], optimizationContext: OptimizationContext): List[AssemblyLine] = {
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val options = optimizationContext.options
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val log = options.log
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val paramVariables = f.params match {
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case NormalParamSignature(List(MemoryVariable(_, typ, _))) if typ.size == 1 =>
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Set[String]()
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case NormalParamSignature(ps) =>
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ps.map(_.name).toSet
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case _ =>
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// assembly functions do not get this optimization
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return code
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}
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val stillUsedVariables = mutable.Set[String]()
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val variablesWithAddressesTaken = mutable.Set[String]()
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code.foreach {
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case AssemblyLine0(_, _, MemoryAddressConstant(th)) => stillUsedVariables += th.name
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case AssemblyLine0(_, _, SubbyteConstant(MemoryAddressConstant(th), _)) => variablesWithAddressesTaken += th.name
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case _ => None
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}
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val localVariables = mutable.Set[Variable]()
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val variablesWithRegisterHint = mutable.Set[String]()
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f.environment.getAllLocalVariables.foreach {
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case v@MemoryVariable(name, typ, alloc@(VariableAllocationMethod.Auto | VariableAllocationMethod.Register)) =>
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if (typ.size == 1 && !paramVariables(name) && stillUsedVariables(name) && !variablesWithAddressesTaken(name) && !v.isVolatile){
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localVariables += v
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if (alloc == VariableAllocationMethod.Register) {
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variablesWithRegisterHint += v.name
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}
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}
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case _ => false
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}
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val variablesWithLifetimes = localVariables.map(v =>
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v.name -> VariableLifetime.apply(v.name, code)
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).toMap
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val removeVariablesForReal = !options.flag(CompilationFlag.InternalCurrentlyOptimizingForMeasurement)
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val costFunction: CyclesAndBytes => Int = if (options.flag(CompilationFlag.OptimizeForSpeed)) _.cycles else _.bytes
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val importances = ReverseFlowAnalyzer.analyze(f, code, optimizationContext)
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val blastProcessing = options.flag(CompilationFlag.OptimizeForSonicSpeed)
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val identityArray = f.environment.maybeGet[ThingInMemory]("identity$").map(MemoryAddressConstant).getOrElse(Constant.Zero)
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val izIsAlwaysZero = !options.flag(CompilationFlag.Emit65CE02Opcodes)
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val featuresForIndices = FeaturesForIndexRegisters(
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blastProcessing = blastProcessing,
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izIsAlwaysZero = izIsAlwaysZero,
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indexRegisterTransfers = options.flag(CompilationFlag.EmitEmulation65816Opcodes),
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functionsSafeForX = optimizationContext.niceFunctionProperties.filter(x => x._1 == MosNiceFunctionProperty.DoesntChangeX).map(_._2),
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functionsSafeForY = optimizationContext.niceFunctionProperties.filter(x => x._1 == MosNiceFunctionProperty.DoesntChangeY).map(_._2),
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functionsSafeForZ = optimizationContext.niceFunctionProperties.filter(x => x._1 == MosNiceFunctionProperty.DoesntChangeIZ).map(_._2),
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identityArray = identityArray,
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log = log
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)
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val tmpUsedLabelList = mutable.ListBuffer[String]()
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code.foreach{
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case AssemblyLine0(op, _, MemoryAddressConstant(Label(l))) if op != Opcode.LABEL => tmpUsedLabelList += l
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case _ =>
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}
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val labelsUsedOnce: Set[String] = tmpUsedLabelList.groupBy(identity).filter(_._2.size == 1).keySet
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val featuresForAcc = FeaturesForAccumulator(
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cmos = options.flag(CompilationFlag.EmitCmosOpcodes),
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safeFunctions = optimizationContext.niceFunctionProperties.filter(x => x._1 == MosNiceFunctionProperty.DoesntChangeA).map(_._2),
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labelsUsedOnce = labelsUsedOnce,
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labelsSyncedAt = Set(),
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log = log
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)
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val xCandidates = variablesWithLifetimes.filter {
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case (vName, range) =>
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importances(range.start).x != Important
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}.flatMap {
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case (vName, range) =>
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canBeInlined(Some(vName), None, None, featuresForIndices, code.zip(importances).slice(range.start, range.end)).map { score =>
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(vName, range, if (variablesWithRegisterHint(vName)) score + CyclesAndBytes(16, 16) else score)
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}
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}
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val yCandidates = variablesWithLifetimes.filter {
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case (vName, range) =>
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importances(range.start).y != Important
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}.flatMap {
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case (vName, range) =>
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canBeInlined(None, Some(vName), None, featuresForIndices, code.zip(importances).slice(range.start, range.end)).map { score =>
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(vName, range, if (variablesWithRegisterHint(vName)) score + CyclesAndBytes(16, 16) else score)
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}
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}
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val zCandidates = if (izIsAlwaysZero) Nil else variablesWithLifetimes.filter {
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case (vName, range) =>
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importances(range.start).iz != Important
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}.flatMap {
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case (vName, range) =>
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canBeInlined(None, None, Some(vName), featuresForIndices, code.zip(importances).slice(range.start, range.end)).map { score =>
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(vName, range, if (variablesWithRegisterHint(vName)) score + CyclesAndBytes(16, 16) else score)
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}
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}
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val aCandidates = variablesWithLifetimes.filter {
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case (vName, range) =>
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importances(range.start).a != Important
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}.flatMap {
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case (vName, range) =>
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canBeInlinedToAccumulator(
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featuresForAcc,
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start = true,
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synced = false,
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vName,
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code.zip(importances).slice(range.start, range.end)).map { score =>
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(vName, range, if (variablesWithRegisterHint(vName)) score + CyclesAndBytes(16, 16) else score)
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}
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}
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// println(s"X: $xCandidates")
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// println(s"Y: $yCandidates")
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// println(s"Z: $zCandidates")
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// println(s"A: $aCandidates")
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val xCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](xCandidates, _._2.start, _._2.end)
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val yCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](yCandidates, _._2.start, _._2.end)
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val zCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](zCandidates, _._2.start, _._2.end)
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val aCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](aCandidates, _._2.start, _._2.end)
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val variants = for {
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vx <- if (options.flag(CompilationFlag.SingleThreaded)) xCandidateSets else xCandidateSets.par
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nx = vx.map(_._1)
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vy <- yCandidateSets
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ny = vy.map(_._1)
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if (nx & ny).isEmpty
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vz <- zCandidateSets
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nz = vz.map(_._1)
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if (nx & nz).isEmpty
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if (ny & nz).isEmpty
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va <- aCandidateSets
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na = va.map(_._1)
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if (nz & na).isEmpty
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if (nx & na).isEmpty
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if (ny & na).isEmpty
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score = vx.toSeq.map(x => costFunction(x._3)).sum +
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vy.toSeq.map(x => costFunction(x._3)).sum +
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va.toSeq.map(x => costFunction(x._3)).sum +
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vz.toSeq.map(x => costFunction(x._3)).sum
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} yield (score, vx, vy, vz, va)
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if (variants.isEmpty) {
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return code
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}
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// variants.foreach(println)
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val (_, bestXs, bestYs, bestZs, bestAs) = variants.maxBy(_._1)
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def reportOptimizedBlock[T](oldCode: List[(AssemblyLine, T)], newCode: List[AssemblyLine]): Unit = {
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if (log.traceEnabled) {
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oldCode.foreach(l => log.trace(l._1.toString))
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log.trace(" ↓")
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newCode.foreach(l => log.trace(l.toString))
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}
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}
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if (bestXs.nonEmpty || bestYs.nonEmpty || bestZs.nonEmpty || bestAs.nonEmpty) {
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val output = ListBuffer[AssemblyLine]()
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var i = 0
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while (i < code.length) {
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var done = false
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bestXs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register X")
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val oldCode = code.zip(importances).slice(range.start, range.end)
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val newCode = inlineVars(Some(v), None, None, None, featuresForIndices, oldCode).result
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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if (removeVariablesForReal && contains(range, variablesWithLifetimes(v))) {
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f.environment.removeVariable(v)
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}
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done = true
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}
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if (!done) {
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bestYs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register Y")
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val oldCode = code.zip(importances).slice(range.start, range.end)
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val newCode = inlineVars(None, Some(v), None, None, featuresForIndices, oldCode).result
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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if (removeVariablesForReal && contains(range, variablesWithLifetimes(v))) {
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f.environment.removeVariable(v)
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}
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done = true
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}
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}
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if (!done) {
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bestZs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register Z")
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val oldCode = code.zip(importances).slice(range.start, range.end)
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val newCode = inlineVars(None, None, Some(v), None, featuresForIndices, oldCode).result
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reportOptimizedBlock(oldCode, newCode)
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output ++= newCode
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i = range.end
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if (removeVariablesForReal && contains(range, variablesWithLifetimes(v))) {
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f.environment.removeVariable(v)
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}
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done = true
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}
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}
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if (!done) {
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bestAs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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log.debug(s"Inlining $v to register A")
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val oldCode = code.zip(importances).slice(range.start, range.end)
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val newCode = inlineVars(None, None, None, Some(v), featuresForIndices, oldCode).result
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reportOptimizedBlock(code.zip(importances), newCode)
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output ++= newCode
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i = range.end
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if (removeVariablesForReal && contains(range, variablesWithLifetimes(v))) {
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f.environment.removeVariable(v)
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}
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done = true
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}
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}
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if (!done) {
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output += code(i)
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i += 1
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}
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}
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output.toList
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} else {
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code
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}
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}
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def contains(outer: Range, inner: Range): Boolean = {
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outer.contains(inner.start) && outer.contains(inner.end - 1)
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}
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// TODO: STA has different flag behaviour than TAX, keep it in mind!
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def canBeInlined(xCandidate: Option[String], yCandidate: Option[String], zCandidate: Option[String], features: FeaturesForIndexRegisters, lines: List[(AssemblyLine, CpuImportance)]): Option[CyclesAndBytes] = {
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val vx = xCandidate.getOrElse("-")
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val vy = yCandidate.getOrElse("-")
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val vz = zCandidate.getOrElse("-")
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lines match {
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case (AssemblyLine0(_, Immediate, MemoryAddressConstant(th)), _) :: xs
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if th.name == vx || th.name == vy || th.name == vz =>
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// if an address of a variable is used, then that variable cannot be assigned to a register
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None
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case (AssemblyLine0(_, Immediate, SubbyteConstant(MemoryAddressConstant(th), _)), _) :: xs
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if th.name == vx || th.name == vy || th.name == vz =>
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// if an address of a variable is used, then that variable cannot be assigned to a register
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None
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case (AssemblyLine0(LDX | STX, AbsoluteY | ZeroPageY | IndexedY | IndexedSY | IndexedZ, _), _) :: xs if xCandidate.isDefined =>
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None
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case (AssemblyLine0(LDY | STY, AbsoluteX | ZeroPageX | IndexedX | LongAbsoluteX | IndexedZ, _), _) :: xs if yCandidate.isDefined =>
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None
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case (AssemblyLine0(LDZ | STZ, AbsoluteX | ZeroPageX | IndexedX | LongAbsoluteX | AbsoluteY | ZeroPageY | IndexedY | IndexedSY, _), _) :: xs if zCandidate.isDefined =>
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None
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case (AssemblyLine0(_, AbsoluteX | AbsoluteY | LongAbsoluteX |
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ZeroPageX | ZeroPageY |
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IndexedY | IndexedX | IndexedZ |
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LongIndexedY | LongIndexedZ |
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Indirect | LongIndirect |
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AbsoluteIndexedX, MemoryAddressConstant(th)), _) :: xs =>
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// if a variable is used as an array or a pointer, then it cannot be assigned to a register
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if (th.name == vx || th.name == vy || th.name == vz) {
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None
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} else {
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canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
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}
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case (AssemblyLine0(SEP | REP, Immediate, NumericConstant(nn, _)), _) :: xs =>
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if ((nn & 0x10) == 0) canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
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else None
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case (AssemblyLine0(SEP | REP, _, _), _) :: xs => None
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case (AssemblyLine0(STY | LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vx && (features.indexRegisterTransfers) =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(STX | LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vy && (features.indexRegisterTransfers) =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(AssemblyLine0(LDA | STA | ADC | SBC | ORA | EOR | AND | CMP, AbsoluteY, _), f) :: xs if th.name == vx && f.y == Unimportant =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(AssemblyLine0(LDA | STA | ADC | SBC | ORA | EOR | AND | CMP, AbsoluteX, _), f) :: xs if th.name == vy && f.x == Unimportant =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(AssemblyLine0(SEC | CLC, _, _), _) ::
|
|
(AssemblyLine0(LDA | STA | ADC | SBC | ORA | EOR | AND | CMP, AbsoluteY, _), f) :: xs if th.name == vx && f.y == Unimportant =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(AssemblyLine0(SEC | CLC, _, _), _) ::
|
|
(AssemblyLine0(LDA | STA | ADC | SBC | ORA | EOR | AND | CMP, AbsoluteX, _), f) :: xs if th.name == vy && f.x == Unimportant =>
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
|
|
case (AssemblyLine0(STY | LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vx => None
|
|
|
|
case (AssemblyLine0(STX | LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vy => None
|
|
|
|
case (AssemblyLine(op, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs
|
|
if opcodesIdentityTable(op) && features.blastProcessing =>
|
|
if (th.name == vx || th.name == vy) {
|
|
if (elidability == Elidability.Elidable) canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 0, cycles = -1))
|
|
else None
|
|
} else {
|
|
if (th.name == vz) None
|
|
else canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine0(opcode, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if th.name == vx && (opcode == LDY || opcode == LDZ || opcodesThatCannotBeUsedWithIndexRegistersAsParameters(opcode)) =>
|
|
// if a variable is used by some opcodes, then it cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine0(opcode, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if th.name == vy && (opcode == LDX || opcode == LAX || opcode == LDZ || opcodesThatCannotBeUsedWithIndexRegistersAsParameters(opcode)) =>
|
|
// if a variable is used by some opcodes, then it cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine0(opcode, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if th.name == vz && (opcode == LDX || opcode == LDY || opcodesThatCannotBeUsedWithIndexRegistersAsParameters(opcode)) =>
|
|
// if a variable is used by some opcodes, then it cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), imp) :: xs
|
|
if xCandidate.isDefined =>
|
|
// if a register is populated with a different variable, then this variable cannot be assigned to that register
|
|
// removing LDX saves 3 cycles
|
|
if (elidability == Elidability.Elidable && th.name == vx) {
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 1, cycles = 2))
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LAX, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs
|
|
if xCandidate.isDefined =>
|
|
// LAX = LDX-LDA, and since LDX simplifies to nothing and LDA simplifies to TXA,
|
|
// LAX simplifies to TXA, saving two bytes
|
|
if (elidability == Elidability.Elidable && th.name == vx) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), imp) :: xs if yCandidate.isDefined =>
|
|
// if a register is populated with a different variable, then this variable cannot be assigned to that register
|
|
// removing LDX saves 3 bytes
|
|
// sometimes that LDX has to be converted into CPX#0
|
|
if (elidability == Elidability.Elidable && th.name == vy) {
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 1, cycles = 2))
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LDZ, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), imp) :: xs if zCandidate.isDefined =>
|
|
if (elidability == Elidability.Elidable && th.name == vz) {
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 1, cycles = 2))
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(LDX, _, _), _) :: xs if xCandidate.isDefined =>
|
|
// if a register is populated with something else than a variable, then no variable cannot be assigned to that register
|
|
None
|
|
|
|
case (AssemblyLine0(LDY, _, _), _) :: xs if yCandidate.isDefined =>
|
|
// if a register is populated with something else than a variable, then no variable cannot be assigned to that register
|
|
None
|
|
|
|
case (AssemblyLine0(LDZ, _, _), _) :: xs if zCandidate.isDefined =>
|
|
// if a register is populated with something else than a variable, then no variable cannot be assigned to that register
|
|
None
|
|
|
|
case (AssemblyLine(LDA, _, _, elidability, _), _) :: (AssemblyLine(op, Absolute | ZeroPage, MemoryAddressConstant(th), elidability2, _), _) :: xs
|
|
if opcodesCommutative(op) =>
|
|
// LDAw/ANDx -> TXA/ANDw
|
|
if (th.name == vx || th.name == vy) {
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable) canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
else None
|
|
} else {
|
|
if (th.name == vz) None
|
|
else canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine(LDA, _, _, elidability, _), _) :: (AssemblyLine0(CLC, _, _),_) :: (AssemblyLine(op, Absolute | ZeroPage, MemoryAddressConstant(th), elidability2, _), _) :: xs
|
|
if opcodesCommutative(op) =>
|
|
if (th.name == vx || th.name == vy) {
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable) canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
else None
|
|
} else {
|
|
if (th.name == vz) None
|
|
else canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: (AssemblyLine(TAX, _, _, elidability2, _), _) :: xs
|
|
if xCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAX not after LDA of that variable
|
|
// but LDA-TAX can be simplified to TXA
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable && th.name == vx) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: (AssemblyLine(TAY, _, _, elidability2, _), _) :: xs
|
|
if yCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAY not after LDA of that variable
|
|
// but LDA-TAY can be simplified to TYA
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable && th.name == vy) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: (AssemblyLine(TAZ, _, _, elidability2, _), _) :: xs
|
|
if zCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAZ not after LDA of that variable
|
|
// but LDA-TAZ can be simplified to TZA
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable && th.name == vy) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(LDA | STA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs =>
|
|
// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
|
|
if (th.name == vy || th.name == vx || th.name == vz) {
|
|
if (elidability == Elidability.Elidable) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine(INC | DEC, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs =>
|
|
// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
|
|
if (th.name == vy || th.name == vx || th.name == vz) {
|
|
if (elidability == Elidability.Elidable) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine(STZ, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs =>
|
|
// changing STZ->LDX saves 1 byte
|
|
if (th.name == vy || th.name == vx) {
|
|
if (elidability == Elidability.Elidable && features.izIsAlwaysZero) {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs).map(_ + CyclesAndBytes(bytes = 1, cycles = 2))
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case (AssemblyLine0(TAX, _, _), _) :: xs if xCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAX not after LDA of that variable
|
|
None
|
|
|
|
case (AssemblyLine0(TAY, _, _), _) :: xs if yCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAY not after LDA of that variable
|
|
None
|
|
|
|
case (AssemblyLine0(TAZ, _, _), _) :: xs if zCandidate.isDefined =>
|
|
// a variable cannot be inlined if there is TAZ not after LDA of that variable
|
|
None
|
|
|
|
case (AssemblyLine0(LABEL, _, _), _) :: xs =>
|
|
// labels always end the initial section
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
|
|
case (AssemblyLine0(JSR, Absolute | LongAbsolute, MemoryAddressConstant(th)), _) :: xs =>
|
|
if (
|
|
xCandidate.isDefined && features.functionsSafeForX(th.name) ||
|
|
yCandidate.isDefined && features.functionsSafeForY(th.name) ||
|
|
zCandidate.isDefined && features.functionsSafeForZ(th.name)
|
|
) canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
else None
|
|
|
|
case (x, _) :: xs =>
|
|
if (xCandidate.isDefined && opcodesThatAlwaysPrecludeXAllocation(x.opcode)) {
|
|
None
|
|
} else if (yCandidate.isDefined && opcodesThatAlwaysPrecludeYAllocation(x.opcode)) {
|
|
None
|
|
} else if (zCandidate.isDefined && opcodesThatAlwaysPrecludeZAllocation(x.opcode)) {
|
|
None
|
|
} else {
|
|
canBeInlined(xCandidate, yCandidate, zCandidate, features, xs)
|
|
}
|
|
|
|
case Nil => Some(CyclesAndBytes.Zero)
|
|
}
|
|
}
|
|
|
|
private def isReturn(code: List[(AssemblyLine, CpuImportance)], allowLdx: Boolean = true): Boolean = {
|
|
import Opcode._
|
|
code match {
|
|
case (AssemblyLine0(LDX, Immediate, _), _) :: xs => allowLdx && isReturn(xs, allowLdx = false)
|
|
case (AssemblyLine0(RTS | RTI | RTL, _, _), _) :: _ => true
|
|
case (AssemblyLine0(op, _, _), _) :: xs if OpcodeClasses.NoopDiscardsFlags(op) => isReturn(xs, allowLdx = false)
|
|
case _ => false
|
|
}
|
|
}
|
|
|
|
def isAllVeryNiceForA(label: String, code: List[(AssemblyLine, CpuImportance)]): (Boolean, List[(AssemblyLine, CpuImportance)]) = {
|
|
code match {
|
|
case (AssemblyLine0(op, _, MemoryAddressConstant(Label(l))), _) :: xs if l == label => (true, xs)
|
|
case (AssemblyLine0(op, _, _), _) :: xs if opcodesThatNeverPrecludeAAllocation(op) => isAllVeryNiceForA(label, xs)
|
|
case _ => (false, Nil)
|
|
}
|
|
}
|
|
|
|
def syncsSoon(candidate: String, code: List[(AssemblyLine, CpuImportance)]): Boolean = {
|
|
code match {
|
|
case (AssemblyLine0(op, _, _), _) :: xs if opcodesThatNeverPrecludeAAllocation(op) => syncsSoon(candidate, xs)
|
|
case (AssemblyLine0(LDA, ZeroPage | Absolute | LongAbsolute, MemoryAddressConstant(th)), _) :: xs if th.name == candidate => true
|
|
case _ => false
|
|
}
|
|
}
|
|
|
|
def canBeInlinedToAccumulator(features: FeaturesForAccumulator, start: Boolean, synced: Boolean, candidate: String, lines: List[(AssemblyLine, CpuImportance)]): Option[CyclesAndBytes] = {
|
|
lines match {
|
|
|
|
case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, _), _) :: xs
|
|
if th.name == candidate && start || synced =>
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
|
|
|
|
case (AssemblyLine0(LABEL, _, MemoryAddressConstant(Label(l))), _) :: xs =>
|
|
if ((synced || features.labelsSyncedAt(l)) && syncsSoon(candidate, xs)) {
|
|
canBeInlinedToAccumulator(features, start = start, synced = synced, candidate, xs)
|
|
} else {
|
|
if (features.labelsUsedOnce(l)) {
|
|
val (isNice, tail) = isAllVeryNiceForA(l, xs)
|
|
if (isNice) {
|
|
canBeInlinedToAccumulator(features, start = start, synced = synced, candidate, tail)
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
case (AssemblyLine0(op, Absolute | Relative | LongRelative, MemoryAddressConstant(Label(l))), _) :: xs if OpcodeClasses.AllDirectJumps(op) =>
|
|
if (synced) {
|
|
canBeInlinedToAccumulator(features.addSafeLabel(l), start = start, synced = synced, candidate, xs)
|
|
} else {
|
|
if (features.labelsUsedOnce(l)) {
|
|
val (isNice, tail) = isAllVeryNiceForA(l, xs)
|
|
if (isNice) {
|
|
canBeInlinedToAccumulator(features, start = start, synced = synced, candidate, tail)
|
|
} else {
|
|
None
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
case (AssemblyLine0(_, TripleAbsolute | ZeroPageWithRelative, _), _) :: xs =>
|
|
// TODO: maybe improve later?
|
|
None
|
|
|
|
case (AssemblyLine0(LABEL, _, _), _) :: xs =>
|
|
None
|
|
|
|
case (AssemblyLine0(op, _, _),_) :: xs if opcodesThatAlwaysPrecludeAAllocation(op) =>
|
|
None
|
|
|
|
case (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if th.name == candidate && opcodesThatCannotBeUsedWithAccumulatorAsParameter(op) =>
|
|
// if a variable is used by some opcodes, then it cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine0(_, Immediate, SubbyteConstant(MemoryAddressConstant(th), _)), _) :: xs
|
|
if th.name == candidate =>
|
|
// if an address of a variable is used, then that variable cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine0(_, AbsoluteX | AbsoluteY | ZeroPageX | ZeroPageY | IndexedY | IndexedX | IndexedZ | Indirect | AbsoluteIndexedX, MemoryAddressConstant(th)), _) :: xs
|
|
if th.name == candidate =>
|
|
// if a variable is used as an array or a pointer, then it cannot be assigned to a register
|
|
None
|
|
|
|
case (AssemblyLine0(SEP | REP, Immediate, NumericConstant(nn, _)), _) :: xs =>
|
|
if ((nn & 0x20) == 0) canBeInlinedToAccumulator(features, start = false, synced = synced, candidate, xs)
|
|
else None
|
|
|
|
case (AssemblyLine0(SEP | REP, _, _), _) :: xs => None
|
|
|
|
case (AssemblyLine(STA, _, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == candidate =>
|
|
if (synced && elidability == Elidability.Elidable) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(DCP, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == candidate =>
|
|
if (synced) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs)
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(STA | SAX, _, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name != candidate =>
|
|
if (synced) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs)
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(STA | SAX, _, NumericConstant(_, _)), _) :: xs =>
|
|
if (synced) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs)
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(SAX, _, MemoryAddressConstant(th)), _) :: xs if th.name == candidate =>
|
|
// if XAA had stable magic $FF, then SAXv/LDAv would correspond to XAA#ff
|
|
// but there's no point in even thinking about that
|
|
None
|
|
|
|
case (AssemblyLine0(TAX | TAY, _, _),_) :: xs =>
|
|
if (synced) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs)
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(LDA | TYA | TXA | TZA | CLA, _, _), _) :: xs if isReturn(xs) =>
|
|
canBeInlinedToAccumulator(features, start = start, synced = synced, candidate, xs)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, _), imp) :: xs
|
|
if th.name == candidate =>
|
|
// removing LDA saves 3 bytes
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
} else {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 1, cycles = 2))
|
|
}
|
|
|
|
case (AssemblyLine(LDA, _, _, elidability, _), _) :: (AssemblyLine(op, Absolute | ZeroPage, MemoryAddressConstant(th), elidability2, _), _) :: xs
|
|
if opcodesCommutative(op) && synced =>
|
|
if (th.name == candidate) {
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable) canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
else None
|
|
} else canBeInlinedToAccumulator(features, start = false, synced = synced, candidate, xs)
|
|
|
|
case (AssemblyLine(LDA, _, _, elidability, _), _) :: (AssemblyLine0(CLC, _, _),_) :: (AssemblyLine(op, Absolute | ZeroPage, MemoryAddressConstant(th), elidability2, _), _) :: xs
|
|
if opcodesCommutative(op) && synced =>
|
|
if (th.name == candidate) {
|
|
if (elidability == Elidability.Elidable && elidability2 == Elidability.Elidable) canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 3, cycles = 4))
|
|
else None
|
|
} else canBeInlinedToAccumulator(features, start = false, synced = synced, candidate, xs)
|
|
|
|
case (AssemblyLine(LDX | LDY | LAX, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs
|
|
if th.name == candidate && synced =>
|
|
// converting a load into a transfer saves 2 bytes
|
|
if (elidability == Elidability.Elidable) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = true, candidate, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(LDA | LAX, _, _),_) :: xs =>
|
|
// if a register is populated with something else than a variable, then no variable cannot be assigned to that register
|
|
None
|
|
|
|
case (AssemblyLine(ASL | LSR | ROR | ROL, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs
|
|
if th.name == candidate =>
|
|
if (elidability == Elidability.Elidable) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = false, candidate, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(INC | DEC, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs
|
|
if th.name == candidate =>
|
|
if (features.cmos && elidability == Elidability.Elidable) {
|
|
canBeInlinedToAccumulator(features, start = false, synced = false, candidate, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine(TXA | TYA, _, _, elidability, _), imp) :: xs =>
|
|
if (imp.a == Unimportant && imp.c == Unimportant && imp.v == Unimportant && elidability == Elidability.Elidable) {
|
|
// TYA/TXA has to be converted to CPY#0/CPX#0
|
|
canBeInlinedToAccumulator(features, start = false, synced = false, candidate, xs).map(_ + CyclesAndBytes(bytes = -1, cycles = 0))
|
|
} else {
|
|
None
|
|
}
|
|
|
|
case (AssemblyLine0(JSR, Absolute | LongAbsolute, MemoryAddressConstant(th)), _) :: xs =>
|
|
if (features.safeFunctions(th.name)) canBeInlinedToAccumulator(features, start = false, synced = synced, candidate, xs)
|
|
else None
|
|
|
|
case (x, _) :: xs => canBeInlinedToAccumulator(features, start = false, synced = synced && OpcodeClasses.AllLinear(x.opcode), candidate, xs)
|
|
|
|
case Nil => Some(CyclesAndBytes.Zero)
|
|
}
|
|
}
|
|
|
|
def isNot(v: String, param: Constant): Boolean = param match {
|
|
case MemoryAddressConstant(th) => th.name != v
|
|
case CompoundConstant(_, MemoryAddressConstant(th), _) => th.name != v
|
|
case _ => true
|
|
}
|
|
|
|
def inlineVars(xCandidate: Option[String],
|
|
yCandidate: Option[String],
|
|
zCandidate: Option[String],
|
|
aCandidate: Option[String],
|
|
features: FeaturesForIndexRegisters,
|
|
lines: List[(AssemblyLine, CpuImportance)]): TailRec[List[AssemblyLine]] = {
|
|
// only one of these will be defined:
|
|
val vx = xCandidate.getOrElse("-")
|
|
val vy = yCandidate.getOrElse("-")
|
|
val vz = zCandidate.getOrElse("-")
|
|
val va = aCandidate.getOrElse("-")
|
|
lines match {
|
|
case (AssemblyLine(INC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map( AssemblyLine.implied(INX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(INC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(INY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(INC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vz =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(INZ).pos(s) :: _)
|
|
|
|
case (AssemblyLine(DEC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(DEX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(DEC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(DEY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(DEC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vz =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(DEZ).pos(s) :: _)
|
|
|
|
case (AssemblyLine(opcode@(DEC | INC | ROL | ROR | ASL | LSR), Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(opcode).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
|
|
if th.name == vx =>
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs))
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPX, 0).pos(s) :: _)
|
|
}
|
|
|
|
case (AssemblyLine(LAX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: _)
|
|
|
|
case (l@AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesIdentityTable(op) && th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l.copy(addrMode = AbsoluteX, parameter = features.identityArray) :: _)
|
|
|
|
case (l@AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesIdentityTable(op) && th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l.copy(addrMode = AbsoluteY, parameter = features.identityArray) :: _)
|
|
|
|
case (l@AssemblyLine0(LDA | TYA | TXA | TZA | CLA, _, _), _) :: xs if aCandidate.isDefined && isReturn(xs) =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l :: _)
|
|
|
|
case (l@AssemblyLine0(LDA, _, _), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l.copy(opcode = op) :: _)
|
|
|
|
case (l@AssemblyLine0(LDA, _, _), _) :: (clc@AssemblyLine0(CLC, _, _), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(clc :: l.copy(opcode = op) :: _)
|
|
|
|
case (l@AssemblyLine(LDA, _, _, _, s), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: l.copy(opcode = op) :: _)
|
|
|
|
case (l@AssemblyLine(LDA, _, _, _, s), _) :: (clc@AssemblyLine0(CLC, _, _), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: clc :: l.copy(opcode = op) :: _)
|
|
|
|
case (l@AssemblyLine(LDA, _, _, _, s), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s) :: l.copy(opcode = op) :: _)
|
|
|
|
case (l@AssemblyLine(LDA, _, _, _, s), _) :: (clc@AssemblyLine0(CLC, _, _), _) :: (AssemblyLine0(op, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs
|
|
if opcodesCommutative(op) && th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s) :: clc :: l.copy(opcode = op) :: _)
|
|
|
|
case (AssemblyLine(LDA | STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
|
|
if th.name == va =>
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CMP, 0).pos(s) :: _)
|
|
}
|
|
|
|
case (AssemblyLine(LAX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
|
|
if th.name == vy =>
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPY, 0).pos(s) :: _)
|
|
}
|
|
|
|
case (AssemblyLine(LDZ, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
|
|
if th.name == vz =>
|
|
if (imp.z == Unimportant && imp.n == Unimportant) {
|
|
inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPZ, 0).pos(s) :: _)
|
|
}
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s), _) :: (AssemblyLine(TAX, _, _, Elidability.Elidable, _), _) :: xs
|
|
if th.name == vx =>
|
|
// these TXA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s), _) :: (AssemblyLine(TAY, _, _, Elidability.Elidable, _), _) :: xs
|
|
if th.name == vy =>
|
|
// these TYA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s), _) :: (AssemblyLine(TAZ, _, _, Elidability.Elidable, _), _) :: xs
|
|
if th.name == vz =>
|
|
// these TZA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TZA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s), _) :: (AssemblyLine(TXA, _, _, Elidability.Elidable, _), _) :: xs
|
|
if th.name == va =>
|
|
// these TAX's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, _), _) :: (AssemblyLine(TYA, _, _, Elidability.Elidable, _), _) :: xs
|
|
if th.name == va =>
|
|
// these TAY's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAY) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s1), _) :: (AssemblyLine(CMP, am, param, Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vx && CpxyzAddrModes(am) && isNot(vx, param) =>
|
|
// ditto
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s1) :: AssemblyLine(CPX, am, param).pos(s2) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s1), _) :: (AssemblyLine(CMP, am, param, Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vy && CpxyzAddrModes(am) && isNot(vx, param) =>
|
|
// ditto
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s1) :: AssemblyLine(CPY, am, param).pos(s2) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s1), _) :: (AssemblyLine(CMP, am, param, Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vy && CpxyzAddrModes(am) && isNot(vx, param) =>
|
|
// ditto
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TZA).pos(s1) :: AssemblyLine(CPZ, am, param).pos(s2) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx && features.indexRegisterTransfers =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy && features.indexRegisterTransfers =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYX).pos(s) :: _)
|
|
|
|
case (l0@AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(l1@AssemblyLine0(LDA | STA | ADC | SBC | AND | ORA | EOR | CMP, AbsoluteY, _), f):: xs
|
|
if th.name == vx =>
|
|
if (l1.opcode != STA || f.n == Unimportant && f.z == Unimportant) {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l1.copy(addrMode = AbsoluteX) :: _)
|
|
} else if (f.c == Unimportant) {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPX, 0).pos(l0.source) :: l1.copy(addrMode = AbsoluteX) :: _)
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(INX).pos(l0.source) :: AssemblyLine.implied(DEX).pos(l0.source) :: l1.copy(addrMode = AbsoluteX) :: _)
|
|
}
|
|
|
|
|
|
case (l0@AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(l1@AssemblyLine0(LDA | STA | ADC | SBC | AND | ORA | EOR | CMP, AbsoluteX, _), f):: xs
|
|
if th.name == vy =>
|
|
if (l1.opcode != STA || f.n == Unimportant && f.z == Unimportant) {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l1.copy(addrMode = AbsoluteY) :: _)
|
|
} else if (f.c == Unimportant) {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPY, 0).pos(l0.source) :: l1.copy(addrMode = AbsoluteY) :: _)
|
|
} else {
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(INY).pos(l0.source) :: AssemblyLine.implied(DEY).pos(l0.source) :: l1.copy(addrMode = AbsoluteY) :: _)
|
|
}
|
|
|
|
case (l0@AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(l5@AssemblyLine0(SEC | CLC, _, _), _) ::
|
|
(l1@AssemblyLine0(LDA | STA | ADC | SBC | AND | ORA | EOR | CMP, AbsoluteY, _), _):: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l5 :: l1.copy(addrMode = AbsoluteX) :: _)
|
|
|
|
case (l0@AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) ::
|
|
(l5@AssemblyLine0(SEC | CLC, _, _), _) ::
|
|
(l1@AssemblyLine0(LDA | STA | ADC | SBC | AND | ORA | EOR | CMP, AbsoluteX, _), _):: xs
|
|
if th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(l5 :: l1.copy(addrMode = AbsoluteY) :: _)
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx => features.log.fatal("Unexpected LDY")
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy => features.log.fatal("Unexpected LDX")
|
|
|
|
case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vz =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TZA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(LDA, am, param, Elidability.Elidable, s1), _) :: (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vx && LdxAddrModes(am) =>
|
|
// these TXA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine(LDX, am, param).pos(s1, s2) :: AssemblyLine.implied(TXA).pos(s1, s2) :: _)
|
|
|
|
case (AssemblyLine(LDA, am, param, Elidability.Elidable, s1), _) :: (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vy && LdyAddrModes(am) =>
|
|
// these TYA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine(LDY, am, param).pos(s1, s2) :: AssemblyLine.implied(TYA).pos(s1, s2) :: _)
|
|
|
|
case (AssemblyLine(LDA, am, param, Elidability.Elidable, s1), _) :: (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), Elidability.Elidable, s2), _) :: xs
|
|
if th.name == vz && LdzAddrModes(am) =>
|
|
// these TZA's may get optimized away by a different optimization
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine(LDZ, am, param).pos(s1, s2) :: AssemblyLine.implied(TZA).pos(s1, s2) :: _)
|
|
|
|
case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vz =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TAZ).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYA).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy && features.indexRegisterTransfers =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TXY).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx && features.indexRegisterTransfers =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TYX).pos(s) :: _)
|
|
|
|
case (AssemblyLine(STX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy => features.log.fatal("Unexpected STX")
|
|
|
|
case (AssemblyLine(STY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx => features.log.fatal("Unexpected STY")
|
|
|
|
case (AssemblyLine(STZ, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vx =>
|
|
if (features.izIsAlwaysZero) tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(LDX, 0).pos(s) :: _)
|
|
else features.log.fatal("Unexpected STZ")
|
|
|
|
case (AssemblyLine(STZ, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == vy =>
|
|
if (features.izIsAlwaysZero) tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(LDY, 0).pos(s) :: _)
|
|
else features.log.fatal("Unexpected STZ")
|
|
|
|
case (AssemblyLine(STZ, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
|
|
if th.name == va =>
|
|
if (features.izIsAlwaysZero) tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(LDA, 0).pos(s) :: _)
|
|
else tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.implied(TZA).pos(s) :: _)
|
|
|
|
case (AssemblyLine0(TAX, _, _), _) :: xs if xCandidate.isDefined =>
|
|
features.log.fatal("Unexpected TAX")
|
|
|
|
case (AssemblyLine0(TAY, _, _), _) :: xs if yCandidate.isDefined =>
|
|
features.log.fatal("Unexpected TAY")
|
|
|
|
case (AssemblyLine0(TAZ, _, _), _) :: xs if zCandidate.isDefined =>
|
|
features.log.fatal("Unexpected TAZ")
|
|
|
|
case (AssemblyLine(TXA, _, _, _, s), _) :: xs if aCandidate.isDefined =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPX, 0).pos(s) :: _)
|
|
|
|
case (AssemblyLine(TYA, _, _, _, s), _) :: xs if aCandidate.isDefined =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPY, 0).pos(s) :: _)
|
|
|
|
case (AssemblyLine(TZA, _, _, _, s), _) :: xs if aCandidate.isDefined =>
|
|
tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(AssemblyLine.immediate(CPZ, 0).pos(s) :: _)
|
|
|
|
case (x, _) :: xs => tailcall(inlineVars(xCandidate, yCandidate, zCandidate, aCandidate, features, xs)).map(x :: _)
|
|
|
|
case Nil => done(Nil)
|
|
}
|
|
}
|
|
|
|
def doesntUseXOrY(am: AddrMode.Value): Boolean = am match {
|
|
case Immediate | WordImmediate | ZeroPage | Absolute | LongAbsolute | Relative | LongRelative | Indirect | LongIndirect | Stack | IndexedZ => true
|
|
case _ => false
|
|
}
|
|
}
|