mirror of https://github.com/KarolS/millfork.git
243 lines
13 KiB
Scala
243 lines
13 KiB
Scala
package millfork.assembly.opt
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import millfork.assembly.{AddrMode, AssemblyLine, Opcode, State}
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import millfork.assembly.Opcode._
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import millfork.assembly.AddrMode._
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import millfork.assembly.OpcodeClasses._
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import millfork.env.{Constant, NormalFunction, NumericConstant}
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/**
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* These optimizations help on their own, but may prevent other optimizations from triggering.
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*
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* @author Karol Stasiak
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*/
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object LaterOptimizations {
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// This optimization tends to prevent later Variable To Register Optimization,
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// so run this only after it's pretty sure V2RO won't happen any more
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val DoubleLoadToDifferentRegisters = new RuleBasedAssemblyOptimization("Double load to different registers",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA), LDX, TAX),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA), LDY, TAY),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX), LDA, TXA),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY), LDA, TYA),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA), LDX, TAX),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA), LDY, TAY),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX), LDA, TXA),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY), LDA, TYA),
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)
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private def TwoDifferentLoadsWithNoFlagChangeInBetween(opcode1: Opcode.Value, middle: AssemblyLinePattern, opcode2: Opcode.Value, transferOpcode: Opcode.Value) = {
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(HasOpcode(opcode1) & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ChangesMemory) & middle & Not(HasOpcode(opcode2))).* ~
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(HasOpcode(opcode2) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { c =>
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c.init :+ AssemblyLine.implied(transferOpcode)
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}
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}
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private def TwoDifferentLoadsWhoseFlagsWillNotBeChecked(opcode1: Opcode.Value, middle: AssemblyLinePattern, opcode2: Opcode.Value, transferOpcode: Opcode.Value) = {
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((HasOpcode(opcode1) & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ChangesMemory) & middle & Not(HasOpcode(opcode2))).*).capture(2) ~
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(HasOpcode(opcode2) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ (AssemblyLine.implied(transferOpcode) :: ctx.get[List[AssemblyLine]](3))
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}
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}
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private def TwoIdenticalLoadsWithNoFlagChangeInBetween(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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(HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ChangesMemory) & middle & Not(ChangesNAndZ)).* ~
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(HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { c =>
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c.init
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}
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}
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private def TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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(HasOpcode(opcode) & HasAddrMode(Immediate) & MatchParameter(1)) ~
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(LinearOrLabel & middle & Not(ChangesNAndZ)).* ~
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(HasOpcode(opcode) & Elidable & HasAddrMode(Immediate) & MatchParameter(1)) ~~> { c =>
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c.init
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}
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}
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private def TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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((HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~
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(LinearOrLabel & Not(ChangesMemory) & middle).*).capture(2) ~
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(HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ ctx.get[List[AssemblyLine]](3)
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}
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}
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//noinspection ZeroIndexToHead
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private def InterleavedImmediateLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & MatchImmediate(0)) ~
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(Elidable & HasOpcode(store) & HasAddrMode(Absolute) & MatchParameter(8)) ~
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(Elidable & HasOpcode(load) & MatchImmediate(1)) ~
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(Elidable & HasOpcode(store) & HasAddrMode(Absolute) & MatchParameter(9) & DontMatchParameter(8)) ~
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(Elidable & HasOpcode(load) & MatchImmediate(0)) ~~> { c =>
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List(c(2), c(3), c(0), c(1))
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}
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}
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//noinspection ZeroIndexToHead
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private def InterleavedAbsoluteLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & HasAddrMode(Absolute) & MatchParameter(0)) ~
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(Elidable & HasOpcode(store) & HasAddrMode(Absolute) & MatchParameter(8) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(load) & HasAddrMode(Absolute) & MatchParameter(1) & DontMatchParameter(8) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(store) & HasAddrMode(Absolute) & MatchParameter(9) & DontMatchParameter(8) & DontMatchParameter(1) & DontMatchParameter(0)) ~
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(Elidable & HasOpcode(load) & HasAddrMode(Absolute) & MatchParameter(0)) ~~> { c =>
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List(c(2), c(3), c(0), c(1))
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}
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}
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val DoubleLoadToTheSameRegister = new RuleBasedAssemblyOptimization("Double load to the same register",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LAX, Not(ChangesA) & Not(ChangesX)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LAX, Not(ChangesA) & Not(ChangesX)),
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InterleavedImmediateLoads(LDA, STA),
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InterleavedImmediateLoads(LDX, STX),
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InterleavedImmediateLoads(LDY, STY),
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InterleavedAbsoluteLoads(LDA, STA),
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InterleavedAbsoluteLoads(LDX, STX),
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InterleavedAbsoluteLoads(LDY, STY),
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)
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private def pointlessLoadAfterStore(store: Opcode.Value, load: Opcode.Value, addrMode: AddrMode.Value, meantime: AssemblyLinePattern = Anything) = {
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((HasOpcode(store) & HasAddrMode(addrMode) & MatchParameter(1)) ~
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(LinearOrBranch & Not(ChangesA) & Not(ChangesMemory) & meantime).*).capture(2) ~
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(HasOpcode(load) & Elidable & HasAddrMode(addrMode) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ ctx.get[List[AssemblyLine]](3)
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}
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}
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val PointlessLoadAfterStore = new RuleBasedAssemblyOptimization("Pointless load after store",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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pointlessLoadAfterStore(STA, LDA, Absolute),
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pointlessLoadAfterStore(STA, LDA, AbsoluteX, Not(ChangesX)),
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pointlessLoadAfterStore(STA, LDA, AbsoluteY, Not(ChangesY)),
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pointlessLoadAfterStore(STX, LDX, Absolute),
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pointlessLoadAfterStore(STY, LDY, Absolute),
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)
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private val ShiftAddrModes = Set(ZeroPage, ZeroPageX, Absolute, AbsoluteX)
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private val ShiftOpcodes = Set(ASL, ROL, ROR, LSR)
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// LDA-SHIFT-STA is slower than just SHIFT
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// LDA-SHIFT-SHIFT-STA is equally fast as SHIFT-SHIFT, but the latter doesn't use the accumulator
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val PointessLoadingForShifting = new RuleBasedAssemblyOptimization("Pointless loading for shifting",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Not(ReadsA) & Not(OverwritesA)).* ~ OverwritesA ~~> { (code, ctx) =>
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AssemblyLine(ctx.get[Opcode.Value](2), ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) :: code.drop(3)
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},
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Not(ReadsA) & Not(OverwritesA)).* ~ OverwritesA ~~> { (code, ctx) =>
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val shift = AssemblyLine(ctx.get[Opcode.Value](2), ctx.get[AddrMode.Value](0), ctx.get[Constant](1))
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shift :: shift :: code.drop(4)
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}
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)
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// SHIFT-LDA is equally fast as LDA-SHIFT-STA, but can enable further optimizations doesn't use the accumulator
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// LDA-SHIFT-SHIFT-STA is equally fast as SHIFT-SHIFT, but the latter doesn't use the accumulator
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val LoadingAfterShifting = new RuleBasedAssemblyOptimization("Loading after shifting",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcodeIn(ShiftOpcodes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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AssemblyLine(LDA, ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) ::
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AssemblyLine.implied(code.head.opcode) ::
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AssemblyLine(STA, ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) ::
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code.drop(2)
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}
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)
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val UseZeropageAddressingMode = new RuleBasedAssemblyOptimization("Using zeropage addressing mode",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasAddrMode(Absolute) & MatchParameter(0)) ~ Where(ctx => ctx.get[Constant](0).quickSimplify match {
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case NumericConstant(x, _) => (x & 0xff00) == 0
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case _ => false
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}) ~~> (code => code.head.copy(addrMode = ZeroPage) :: Nil)
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)
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val UseXInsteadOfStack = new RuleBasedAssemblyOptimization("Using X instead of stack",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(PHA) & DoesntMatterWhatItDoesWith(State.X)) ~
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(Not(ConcernsStack) & Not(ConcernsX)).capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(Elidable & HasOpcode(PLA)) ~~> (c =>
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AssemblyLine.implied(TAX) :: (c.tail.init :+ AssemblyLine.implied(TXA))
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)
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)
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val UseYInsteadOfStack = new RuleBasedAssemblyOptimization("Using Y instead of stack",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(PHA) & DoesntMatterWhatItDoesWith(State.Y)) ~
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(Not(ConcernsStack) & Not(ConcernsY)).capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(Elidable & HasOpcode(PLA)) ~~> (c =>
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AssemblyLine.implied(TAY) :: (c.tail.init :+ AssemblyLine.implied(TYA))
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)
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)
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// TODO: make it more generic
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val IndexSwitchingOptimization = new RuleBasedAssemblyOptimization("Index switching optimization",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDY) & MatchAddrMode(2) & Not(ReadsX) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesY) & HasAddrMode(AbsoluteY) & SupportsAbsoluteX & Not(ConcernsX)) ~
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(HasOpcode(LDY) & Not(ConcernsX)) ~
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(Linear & Not(ChangesY) & Not(ConcernsX) & HasAddrModeIn(Set(AbsoluteY, IndexedY, ZeroPageY))) ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(2) & Not(ReadsX) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesY) & HasAddrMode(AbsoluteY) & SupportsAbsoluteX & Not(ConcernsX) & DoesntMatterWhatItDoesWith(State.X, State.N, State.Z)) ~~> { (code, ctx) =>
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List(
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code(0).copy(opcode = LDX),
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code(1).copy(addrMode = AbsoluteX),
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code(2),
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code(3),
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code(5).copy(addrMode = AbsoluteX))
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},
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(Elidable & HasOpcode(LDX) & MatchAddrMode(2) & Not(ReadsY) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesX) & HasAddrMode(AbsoluteX) & SupportsAbsoluteY & Not(ConcernsY)) ~
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(HasOpcode(LDX) & Not(ConcernsY)) ~
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(Linear & Not(ChangesX) & Not(ConcernsY) & HasAddrModeIn(Set(AbsoluteX, IndexedX, ZeroPageX, AbsoluteIndexedX))) ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(2) & Not(ReadsY) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesX) & HasAddrMode(AbsoluteX) & SupportsAbsoluteY & Not(ConcernsY) & DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z)) ~~> { (code, ctx) =>
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List(
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code(0).copy(opcode = LDY),
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code(1).copy(addrMode = AbsoluteY),
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code(2),
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code(3),
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code(5).copy(addrMode = AbsoluteY))
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},
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)
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val All = List(
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DoubleLoadToDifferentRegisters,
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DoubleLoadToTheSameRegister,
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IndexSwitchingOptimization,
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PointlessLoadAfterStore,
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PointessLoadingForShifting,
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LoadingAfterShifting,
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UseXInsteadOfStack,
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UseYInsteadOfStack,
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UseZeropageAddressingMode)
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}
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