mirror of
https://github.com/KarolS/millfork.git
synced 2024-06-11 15:29:34 +00:00
381 lines
8.7 KiB
Scala
381 lines
8.7 KiB
Scala
package millfork.assembly.mos
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import java.util.Locale
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import millfork.error.{ConsoleLogger, Logger}
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import millfork.node.Position
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object State extends Enumeration {
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val
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// standard 6502 8-bit registers
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A, X, Y,
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// hi bytes of registers on 65816
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AH, XH, YH,
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// extra 65816 registers
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DP, DBL, PB,
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// extra register of both 65816 (it's called the high byte of DB) and 65CE02 (it's called B)
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DBH,
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// extra 65CE02 register
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IZ,
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// 8 extra HuC6280 MMU registers
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MM,
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// standard 6502 flags
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Z, D, C, N, V,
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// extra 65816 flags; W means X flag, not to confuse with the X register
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E, M, W = Value
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def isAffectedBySepRep(state: State.Value, n: Long): Boolean = {
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state match {
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case C => (n & 1) == 0
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case Z => (n & 2) == 0
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case D => (n & 8) == 0
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case W | XH | YH => (n & 0x10) == 0
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case M => (n & 0x20) == 0
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case V => (n & 0x40) == 0
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case N => (n & 0x80) == 0
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case _ => false
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}
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}
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}
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object Treatment extends Enumeration {
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val Unchanged, Unsure, Changed, Cleared, Set = Value
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implicit class OverriddenValue(val left: Value) extends AnyVal {
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def ~(right: Treatment.Value): Treatment.Value = right match {
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case Unchanged => left
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case Cleared | Set => if (left == Unsure) Changed else right
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case _ => right
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}
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}
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}
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object Opcode extends Enumeration {
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val ADC, AND, ASL,
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BIT, BNE, BEQ, BPL, BMI, BVS, BVC, BCC, BCS, BRK,
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CMP, CPX, CPY, CLV, CLC, CLI, CLD,
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DEC, DEX, DEY,
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EOR,
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INC, INX, INY,
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JMP, JSR,
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LDA, LDX, LDY, LSR,
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NOP,
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ORA,
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PHA, PHP, PLA, PLP,
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ROL, ROR, RTS, RTI,
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SBC, SEC, SED, SEI, STA, STX, STY,
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TAX, TAY, TXA, TXS, TSX, TYA,
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// illegals:
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LXA, XAA, ANC, ARR, ALR, SBX,
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LAX, SAX, RLA, RRA, SLO, SRE, DCP, ISC,
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TAS, LAS, SHX, SHY, AHX, KIL,
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// 65C02:
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STZ, PHX, PHY, PLX, PLY,
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BRA, TRB, TSB, STP, WAI,
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BBR0, BBR1, BBR2, BBR3, BBR4, BBR5, BBR6, BBR7,
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BBS0, BBS1, BBS2, BBS3, BBS4, BBS5, BBS6, BBS7,
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RMB0, RMB1, RMB2, RMB3, RMB4, RMB5, RMB6, RMB7,
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SMB0, SMB1, SMB2, SMB3, SMB4, SMB5, SMB6, SMB7,
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// 65CE02:
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CPZ, LDZ, DEZ, INZ,
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PHW,
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// DEW, INW, ASW, ROW, // aliases for DEC_W, INC_W, ASL_W, ROR_W (?)
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NEG, ASR,
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TAZ, TZA, PHZ, PLZ,
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TSY, TYS,
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TAB, TBA,
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CLE, SEE, // no idea what these do
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BSR,
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MAP, // also called AUG
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//HuC6280:
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CLA, CLX, CLY,
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CSH, CSL,
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SAY, SXY, HuSAX,
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SET,
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ST0, ST1, ST2,
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// BSR, // the same as on 65CE02
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TAM, TMA,
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TAI, TIA, TDD, TIN, TII, // memcpy instructions
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TST,
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//65816:
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BRL,
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COP,
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MVN, MVP, // memcpy instructions
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PEA, PEI, PER,
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PHB, PHD, PHK, PLB, PLD, // there's no PLK for the same reason Intel removed POP CS from 80186
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REP, SEP,
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RTL,
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TCD, TDC, TSC, TCS,
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TXY, TYX, XBA,
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XCE,
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DEC_W, INC_W, ROL_W, ROR_W, ASL_W, LSR_W,
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ORA_W, AND_W, EOR_W, ADC_W, LDA_W, STA_W, CMP_W, SBC_W, STZ_W, BIT_W, TRB_W, TSB_W,
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LDX_W, LDY_W, STX_W, STY_W, CPX_W, CPY_W,
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INX_W, INY_W, DEX_W, DEY_W,
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PHA_W, PLA_W,
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PHX_W, PHY_W, PLY_W, PLX_W,
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DISCARD_AF, DISCARD_XF, DISCARD_YF, CHANGED_MEM,
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BYTE, LABEL = Value
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def widen(opcode: Opcode.Value): Option[Opcode.Value] = opcode match {
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case ORA => Some(ORA_W)
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case AND => Some(AND_W)
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case EOR => Some(EOR_W)
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case ADC => Some(ADC_W)
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case SBC => Some(SBC_W)
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case CMP => Some(CMP_W)
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case LDA => Some(LDA_W)
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case STA => Some(STA_W)
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case STZ => Some(STZ_W)
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case LDX => Some(LDX_W)
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case LDY => Some(LDY_W)
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case STX => Some(STX_W)
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case STY => Some(STY_W)
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case INX => Some(INX_W)
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case INY => Some(INX_W)
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case DEX => Some(DEX_W)
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case DEY => Some(DEY_W)
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case CPX => Some(CPX_W)
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case CPY => Some(CPY_W)
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case INC => Some(INC_W)
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case DEC => Some(DEC_W)
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case ROL => Some(ROL_W)
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case ROR => Some(ROR_W)
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case ASL => Some(ASL_W)
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case LSR => Some(LSR_W)
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case PHA => Some(PHA_W)
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case PLA => Some(PLA_W)
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case PHX => Some(PHX_W)
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case PLX => Some(PLX_W)
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case PHY => Some(PHY_W)
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case PLY => Some(PLY_W)
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case _ => None
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}
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def lookup(opcode: String, position: Option[Position], log: Logger): Opcode.Value = opcode.toUpperCase(Locale.ROOT) match {
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case "ADC" => ADC
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case "AHX" => AHX
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case "ALR" => ALR
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case "ANC" => ANC
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case "AND" => AND
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case "ANE" => XAA
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case "ARR" => ARR
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case "ASL" => ASL
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case "ASO" => SLO
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case "ASR" => ASR
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case "ASW" => ASL_W
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case "AXA" => AHX
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case "AXS" => SBX // could mean SAX
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case "BCC" => BCC
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case "LBCC" => BCC
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case "BCS" => BCS
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case "LBCS" => BCS
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case "BEQ" => BEQ
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case "LBEQ" => BEQ
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case "BIT" => BIT
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case "BMI" => BMI
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case "LBMI" => BMI
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case "BNE" => BNE
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case "LBNE" => BNE
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case "BPL" => BPL
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case "LBPL" => BPL
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case "BRA" => BRA
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case "LBRA" => BRA
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case "BRK" => BRK
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case "BRL" => BRL
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case "BSR" => BSR
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case "LBSR" => BSR
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case "BVC" => BVC
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case "LBVC" => BVC
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case "BVS" => BVS
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case "LBVS" => BVS
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case "CLC" => CLC
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case "CLD" => CLD
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case "CLE" => CLE
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case "CLI" => CLI
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case "CLV" => CLV
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case "CLX" => CLX
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case "CLY" => CLY
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case "CMP" => CMP
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case "COP" => COP
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case "CPX" => CPX
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case "CPY" => CPY
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case "CPZ" => CPZ
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case "CSH" => CSH
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case "CSL" => CSL
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case "DCM" => DCP
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case "DCP" => DCP
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case "DEC" => DEC
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case "DEW" => DEC_W
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case "DEX" => DEX
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case "DEY" => DEY
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case "DEZ" => DEZ
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case "EOR" => EOR
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case "INC" => INC
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case "INS" => ISC
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case "INW" => INC_W
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case "INX" => INX
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case "INY" => INY
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case "INZ" => INZ
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case "ISC" => ISC
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case "JMP" => JMP
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case "JSR" => JSR
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case "KIL" => KIL
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case "LAS" => LAS
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case "LAX" => LAX
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case "LDA" => LDA
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case "LDX" => LDX
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case "LDY" => LDY
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case "LDZ" => LDZ
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case "LSE" => SRE
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case "LSR" => LSR
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case "LXA" => LXA
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case "MAP" => MAP
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case "NEG" => NEG
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case "NOP" => NOP
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case "OAL" => LXA
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case "ORA" => ORA
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case "PEA" => PEA
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case "PEI" => PEI
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case "PER" => PER
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case "PHA" => PHA
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case "PHB" => PHB
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case "PHD" => PHD
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case "PHK" => PHK
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case "PHP" => PHP
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case "PHW" => PHW
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case "PHX" => PHX
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case "PHY" => PHY
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case "PHZ" => PHZ
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case "PLA" => PLA
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case "PLB" => PLB
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case "PLD" => PLD
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case "PLP" => PLP
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case "PLX" => PLX
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case "PLY" => PLY
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case "PLZ" => PLZ
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case "REP" => REP
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case "RLA" => RLA
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case "ROL" => ROL
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case "ROR" => ROR
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case "ROW" => ROL_W
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case "RRA" => RRA
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case "RTI" => RTI
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case "RTL" => RTL
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case "RTS" => RTS
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case "SAX" => SAX // could mean SBX; also, HuC6280 has another SAX that means something else
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case "SAY" => SAY // could mean SHY
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case "SBC" => SBC
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case "SBX" => SBX
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case "SEC" => SEC
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case "SED" => SED
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case "SEE" => SEE
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case "SEI" => SEI
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case "SEP" => SEP
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case "SET" => SET
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case "SHX" => SHX
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case "SHY" => SHY
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case "SLO" => SLO
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case "SRE" => SRE
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case "ST0" => ST0
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case "ST1" => ST1
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case "ST2" => ST2
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case "STA" => STA
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case "STP" => STP
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case "STX" => STX
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case "STY" => STY
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case "STZ" => STZ
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case "SXY" => SXY
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case "TAB" => TAB
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case "TAI" => TAI
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case "TAM" => TAM
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case "TAS" => TAS
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case "TAX" => TAX
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case "TAY" => TAY
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case "TAZ" => TAZ
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case "TBA" => TBA
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case "TCD" => TCD
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case "TDC" => TDC
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case "TDD" => TDD
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case "TCS" => TCS
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case "TIA" => TIA
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case "TII" => TII
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case "TSC" => TSC
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case "TMA" => TMA
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case "TRB" => TRB
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case "TSB" => TSB
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case "TSX" => TSX
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case "TSY" => TSY
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case "TXA" => TXA
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case "TXS" => TXS
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case "TXY" => TXY
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case "TYA" => TYA
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case "TYS" => TYS
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case "TYX" => TYX
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case "TZA" => TZA
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case "WAI" => WAI
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case "XAA" => XAA
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case "XAS" => SHX
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case "XBA" => XBA
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case "XCE" => XCE
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case "BBR0" => BBR0
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case "BBR1" => BBR1
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case "BBR2" => BBR2
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case "BBR3" => BBR3
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case "BBR4" => BBR4
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case "BBR5" => BBR5
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case "BBR6" => BBR6
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case "BBR7" => BBR7
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case "BBS0" => BBS0
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case "BBS1" => BBS1
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case "BBS2" => BBS2
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case "BBS3" => BBS3
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case "BBS4" => BBS4
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case "BBS5" => BBS5
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case "BBS6" => BBS6
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case "BBS7" => BBS7
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case "RMB0" => RMB0
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case "RMB1" => RMB1
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case "RMB2" => RMB2
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case "RMB3" => RMB3
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case "RMB4" => RMB4
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case "RMB5" => RMB5
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case "RMB6" => RMB6
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case "RMB7" => RMB7
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case "SMB0" => SMB0
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case "SMB1" => SMB1
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case "SMB2" => SMB2
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case "SMB3" => SMB3
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case "SMB4" => SMB4
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case "SMB5" => SMB5
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case "SMB6" => SMB6
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case "SMB7" => SMB7
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case "TAI" => TAI
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case "TIA" => TIA
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case "TDD" => TDD
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case "TII" => TII
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case "TIN" => TIN
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case "TST" => TST
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// TODO: add all of those
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case _ =>
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log.error(s"Invalid opcode `$opcode`", position)
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LABEL
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}
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}
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