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99 lines
1.7 KiB
Plaintext
99 lines
1.7 KiB
Plaintext
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#if not(ARCH_6502)
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#warn zp_reg module should be used only on 6502-compatible targets
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#endif
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noinline asm byte __mul_u8u8u8() {
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? LDA #0
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? JMP __mul_u8u8u8_start
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__mul_u8u8u8_add:
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? CLC
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? ADC lo(__reg)
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__mul_u8u8u8_loop:
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? ASL lo(__reg)
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__mul_u8u8u8_start:
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? LSR lo(__reg+1)
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? BCS __mul_u8u8u8_add
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? BNE __mul_u8u8u8_loop
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? RTS
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}
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// divide __reg[0]/__reg[1]
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noinline asm byte __mod_u8u8u8u8() {
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? LDA #0
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? LDX #7
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? CLC
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__divmod_u8u8u8u8_start:
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? ROL lo(__reg)
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? ROL
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? CMP lo(__reg+1)
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? BCC __divmod_u8u8u8u8_skip
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? SBC lo(__reg+1)
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__divmod_u8u8u8u8_skip:
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? DEX
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? BPL __divmod_u8u8u8u8_start
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? ROL lo(__reg)
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? RTS
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}
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asm byte __div_u8u8u8u8() {
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? JSR __mod_u8u8u8u8
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? LDA lo(__reg)
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? RTS
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}
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#if ZPREG_SIZE >= 3
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noinline asm word __mul_u16u8u16() {
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? LDA #0
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? TAX
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? JMP __mul_u16u8u16_start
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__mul_u16u8u16_add:
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? CLC
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? ADC lo(__reg)
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? TAY
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? TXA
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? ADC lo(__reg+1)
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? TAX
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? TYA
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__mul_u16u8u16_loop:
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? ASL lo(__reg)
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? ROL lo(__reg+1)
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__mul_u16u8u16_start:
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? LSR lo(__reg+2)
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? BCS __mul_u16u8u16_add
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? BNE __mul_u16u8u16_loop
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? RTS
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}
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// divide (__reg[1]:__reg[0])/__reg[2]
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noinline asm byte __mod_u16u8u16u8() {
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? LDA #0
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? LDX #15
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? CLC
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__divmod_u16u8u16u8_start:
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? ROL lo(__reg)
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? ROL lo(__reg+1)
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? ROL
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? CMP lo(__reg+2)
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? BCC __divmod_u16u8u16u8_skip
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? SBC lo(__reg+2)
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__divmod_u16u8u16u8_skip:
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? DEX
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? BPL __divmod_u16u8u16u8_start
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? ROL lo(__reg)
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? ROL lo(__reg+1)
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? RTS
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}
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asm word __div_u16u8u16u8() {
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? JSR __mod_u16u8u16u8
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? LDA lo(__reg)
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? LDX lo(__reg+1)
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? RTS
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}
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#endif
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