mirror of https://github.com/KarolS/millfork.git
308 lines
8.6 KiB
Scala
308 lines
8.6 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.assembly.mos.State
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import millfork.assembly.opt._
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object SourceOfNZ {
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val A = SingleStatus(SourceOfNZ(a = true))
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val AW = SingleStatus(SourceOfNZ(aw = true))
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val X = SingleStatus(SourceOfNZ(x = true))
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val Y = SingleStatus(SourceOfNZ(y = true))
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val Z = SingleStatus(SourceOfNZ(iz = true))
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val AX = SingleStatus(SourceOfNZ(a = true, x = true))
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val AY = SingleStatus(SourceOfNZ(a = true, y = true))
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val AZ = SingleStatus(SourceOfNZ(a = true, iz = true))
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val XY = SingleStatus(SourceOfNZ(x = true, y = true))
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}
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case class SourceOfNZ(a: Boolean = false, aw: Boolean = false, x: Boolean = false, y: Boolean = false, iz: Boolean = false) {
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def matches(state: State.Value): Boolean = state match {
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case State.A => a
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case State.X => x
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case State.Y => y
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case State.IZ => iz
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case _ => throw new IllegalArgumentException
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}
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override def toString: String = {
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val builder = new StringBuilder
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if (a) builder += 'A'
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if (aw) builder += 'C'
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if (x) builder += 'X'
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if (y) builder += 'Y'
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if (iz) builder += 'Z'
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if (builder.isEmpty) "?"
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else builder.mkString
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}
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def swapAX: SourceOfNZ = copy(a = x, x = a)
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def swapAY: SourceOfNZ = copy(a = y, y = a)
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def swapXY: SourceOfNZ = copy(y = x, x = y)
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}
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//noinspection RedundantNewCaseClass
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case class CpuStatus(a: Status[Int] = UnknownStatus,
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ah: Status[Int] = UnknownStatus,
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a0: Status[Boolean] = UnknownStatus,
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a7: Status[Boolean] = UnknownStatus,
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x: Status[Int] = UnknownStatus,
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y: Status[Int] = UnknownStatus,
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iz: Status[Int] = UnknownStatus,
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r0: Status[Int] = UnknownStatus,
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r1: Status[Int] = UnknownStatus,
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r2: Status[Int] = UnknownStatus,
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r3: Status[Int] = UnknownStatus,
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src: Status[SourceOfNZ] = UnknownStatus,
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eqSX: Boolean = false,
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eqSpA: Boolean = false,
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eqSpX: Boolean = false,
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z: Status[Boolean] = UnknownStatus,
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n: Status[Boolean] = UnknownStatus,
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c: Status[Boolean] = UnknownStatus,
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v: Status[Boolean] = UnknownStatus,
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d: Status[Boolean] = UnknownStatus,
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m: Status[Boolean] = UnknownStatus,
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w: Status[Boolean] = UnknownStatus
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) {
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def overwriteSp(sp: Boolean): CpuStatus = if (sp && eqSpX) this.copy(eqSpX = false) else this
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// assert(a ne null)
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// assert(ah ne null)
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// assert(x ne null)
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// assert(y ne null)
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// assert(iz ne null)
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// assert(z ne null)
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// assert(n ne null)
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// assert(v ne null)
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// assert(c ne null)
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// assert(d ne null)
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// assert(m ne null)
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// assert(w ne null)
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// assert(a0 ne null)
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// assert(a7 ne null)
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// (a, a7) match {
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// case (SingleStatus(o), SingleStatus(b7)) => if (o.&(0x80).!=(0).!=(b7)) {
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// println(a)
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// println(a7)
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// println(a0)
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// ???
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// }
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// case _ =>
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// }
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// (a, a0) match {
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// case (SingleStatus(o), SingleStatus(b0)) => if (o.&(1).!=(0).!=(b0)) {
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// println(a)
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// println(a7)
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// println(a0)
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// ???
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// }
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// case _ =>
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// }
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override def toString: String = s"A=$a,B=$ah,X=$x,Y=$y,Z=$iz; Z=$z,N=$n,C=$c,V=$v,D=$d,M=$m,X=$w; R0=$r0,R1=$r1,R2=$r2,R3=$r3; A7=$a7,A0=$a0,NZ:$src" +
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(if (eqSX) "; S=X"
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else /*-*/ " ") +
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(if (eqSpX) "; SP=X"
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else /*--*/ " ")
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def aw: Status[Int] = (ah, a) match {
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case (SingleStatus(h), SingleStatus(l)) => SingleStatus(h.&(0xff).<<(8).+(l&0xff))
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case (UnknownStatus, UnknownStatus) => UnknownStatus
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case _ => AnyStatus
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}
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def nz: CpuStatus =
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this.copy(n = AnyStatus, z = AnyStatus)
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def nz(i: Long): CpuStatus =
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this.copy(n = SingleStatus((i & 0x80) != 0), z = SingleStatus((i & 0xff) == 0))
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def nzw(i: Long): CpuStatus =
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this.copy(n = SingleStatus((i & 0x8000) != 0), z = SingleStatus((i & 0xffff) == 0))
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def ~(that: CpuStatus) = new CpuStatus(
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a = this.a ~ that.a,
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ah = this.ah ~ that.ah,
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a7 = this.a7 ~ that.a7,
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a0 = this.a0 ~ that.a0,
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x = this.x ~ that.x,
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y = this.y ~ that.y,
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iz = this.iz ~ that.iz,
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src = this.src ~ that.src,
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eqSX = this.eqSX && that.eqSX,
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eqSpX = this.eqSpX && that.eqSpX,
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z = this.z ~ that.z,
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n = this.n ~ that.n,
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c = this.c ~ that.c,
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v = this.v ~ that.v,
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d = this.d ~ that.d,
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m = this.m ~ that.m,
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w = this.w ~ that.w,
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)
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def hasClear(state: State.Value): Boolean = state match {
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case State.A => a.contains(0)
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case State.AH => ah.contains(0)
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case State.X => x.contains(0)
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case State.Y => y.contains(0)
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case State.IZ => iz.contains(0)
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case State.Z => z.contains(false)
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case State.N => n.contains(false)
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case State.C => c.contains(false)
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case State.V => v.contains(false)
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case State.D => d.contains(false)
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case State.M => m.contains(false)
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case State.W => w.contains(false)
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case _ => false
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}
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def hasSet(state: State.Value): Boolean = state match {
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case State.Z => z.contains(true)
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case State.N => n.contains(true)
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case State.C => c.contains(true)
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case State.V => v.contains(true)
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case State.D => d.contains(true)
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case State.M => m.contains(true)
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case State.W => w.contains(true)
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case _ => false
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}
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def reg(i: Int) : Status[Int] = i match {
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case 0 => r0
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case 1 => r1
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case 2 => r2
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case 3 => r3
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case _ => AnyStatus
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}
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def getReg(i: Option[Int]) : Status[Int] = i match {
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case Some(0) => r0
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case Some(1) => r1
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case Some(2) => r2
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case Some(3) => r3
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case _ => AnyStatus
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}
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def getRegHi(i: Option[Int]) : Status[Int] = i match {
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case Some(0) => r1
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case Some(1) => r2
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case Some(2) => r3
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case _ => AnyStatus
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}
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def setReg(i: Option[Int], status: Status[Int]): CpuStatus = {
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i match {
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case Some(0) => this.copy(r0 = status)
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case Some(1) => this.copy(r1 = status)
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case Some(2) => this.copy(r2 = status)
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case Some(3) => this.copy(r3 = status)
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case _ => this
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}
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}
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}
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object CpuStatus {
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val initialStatusStandard = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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a0 = AnyStatus,
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a7 = AnyStatus,
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialStatusCE = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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a0 = AnyStatus,
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a7 = AnyStatus,
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = AnyStatus,
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusStandard = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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a0 = AnyStatus,
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a7 = AnyStatus,
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d = AnyStatus,
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusCmos = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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a0 = AnyStatus,
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a7 = AnyStatus,
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusCE = CpuStatus(
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a = AnyStatus,
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x = AnyStatus,
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y = AnyStatus,
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c = AnyStatus,
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v = AnyStatus,
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z = AnyStatus,
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n = AnyStatus,
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a0 = AnyStatus,
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a7 = AnyStatus,
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = AnyStatus,
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val emptyStatusStandard = CpuStatus(iz = SingleStatus(0))
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val emptyStatusCE = CpuStatus(iz = AnyStatus)
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} |