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51 lines
2.1 KiB
Scala
51 lines
2.1 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.assembly.mos.AddrMode._
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import millfork.assembly.mos.{AssemblyLine, State}
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import millfork.assembly.mos.Opcode._
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import millfork.env.NumericConstant
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object IdentityPageOptimizations {
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val SimplifiableAccess = new RuleBasedAssemblyOptimization("Simplifiable identity page access",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcode(LDA) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~~> { c =>
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List(AssemblyLine.implied(TXA))
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},
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(Elidable & HasOpcode(LDA) & HasAddrMode(AbsoluteY) & HasIdentityPageParameter) ~~> { c =>
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List(AssemblyLine.implied(TYA))
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},
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)
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val UseInsteadOfStack = new RuleBasedAssemblyOptimization("Use identity page instead of stack",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(PHA)) ~
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(Not(ConcernsX) & Not(ConcernsStack)).*.capture(0) ~
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(Elidable & HasOpcode(TSX) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~
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(Elidable & HasAddrMode(AbsoluteX) & HasParameterWhere{
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case NumericConstant(0x101, _) => true
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case _ => false
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}).capture(1) ~
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(Elidable & HasOpcode(INX)) ~
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(Elidable & HasOpcode(TXS) & DoesntMatterWhatItDoesWith(State.X)) ~~> { (code, ctx) =>
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List(AssemblyLine.implied(TAX)) ++ ctx.get[List[AssemblyLine]](0) ++ List(ctx.get[AssemblyLine](1).copy(parameter = ctx.identityPage))
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},
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(Elidable & HasOpcode(PHA)) ~
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(Not(ConcernsY) & Not(ConcernsStack)).*.capture(0) ~
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(Elidable & HasOpcode(TSX) & HasAddrMode(AbsoluteX) & HasIdentityPageParameter) ~
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(Elidable & HasAddrMode(AbsoluteX) & HasParameterWhere{
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case NumericConstant(0x101, _) => true
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case _ => false
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}).capture(1) ~
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(Elidable & HasOpcode(INX)) ~
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(Elidable & HasOpcode(TXS) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx) =>
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List(AssemblyLine.implied(TAY)) ++ ctx.get[List[AssemblyLine]](0) ++ List(ctx.get[AssemblyLine](1).copy(parameter = ctx.identityPage, addrMode = AbsoluteY))
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},
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)
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val All: List[RuleBasedAssemblyOptimization] = List(
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SimplifiableAccess,
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UseInsteadOfStack)
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}
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