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https://github.com/KarolS/millfork.git
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409 lines
18 KiB
Scala
409 lines
18 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.assembly.mos.AddrMode._
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import millfork.assembly.mos.Opcode._
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import millfork.assembly.mos._
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import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext}
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import millfork.env._
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import millfork.error.Logger
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import millfork.node.MosNiceFunctionProperty
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import millfork.{CompilationFlag, NonOverlappingIntervals}
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import scala.collection.mutable.ListBuffer
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import scala.util.control.TailCalls.{TailRec, done, tailcall}
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/**
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* @author Karol Stasiak
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*/
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object TwoVariablesToIndexRegistersOptimization extends AssemblyOptimization[AssemblyLine] {
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override def minimumRequiredLines: Int = 2
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override def requiredFlags: Set[CompilationFlag.Value] = Set(CompilationFlag.RegisterVariables)
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object CyclesAndBytes {
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val Zero = CyclesAndBytes(0, 0)
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}
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case class CyclesAndBytes(bytes: Int, cycles: Int) {
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def +(that: CyclesAndBytes) = CyclesAndBytes(this.bytes + that.bytes, this.cycles + that.cycles)
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}
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case class FeaturesForIndexRegisters(
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blastProcessing: Boolean,
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izIsAlwaysZero: Boolean,
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indexRegisterTransfers: Boolean,
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functionsSafeForX: Set[String],
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functionsSafeForY: Set[String],
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functionsSafeForZ: Set[String],
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identityArray: Constant,
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log: Logger)
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// If any of these opcodes is present within a method,
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// then it's too hard to assign any variable to a register.
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private val opcodesThatAlwaysPrecludeAllocation = Set(
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JSR,
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STY, TYA, INY, DEY, CPY,
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STX, TXA, INX, DEX, CPX,
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LDX_W, STX_W, CPX_W, DEX_W, INX_W,
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LDY_W, STY_W, CPY_W, DEY_W, INY_W,
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PHX, PLX, PHY, PLY,
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PHX_W, PLX_W, PHY_W, PLY_W,
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SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
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HuSAX, SAY, SXY, TXY, TXY,
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BYTE,
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)
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private val hasBothIndexingModes = Set(
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LDA, STA, CMP, ADC, SBC, EOR, ORA, AND
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)
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override def name = "Allocating two variables to two index registers"
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override def optimize(f: NormalFunction, code: List[AssemblyLine], optimizationContext: OptimizationContext): List[AssemblyLine] = {
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val options = optimizationContext.options
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val log = options.log
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val paramVariables = f.params match {
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case NormalParamSignature(List(MemoryVariable(_, typ, _))) if typ.size == 1 =>
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Set[String]()
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case NormalParamSignature(ps) =>
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ps.map(_.name).toSet
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case _ =>
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// assembly functions do not get this optimization
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return code
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}
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val stillUsedVariables = code.flatMap {
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case AssemblyLine0(_, _, MemoryAddressConstant(th)) => Some(th.name)
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case _ => None
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}.toSet
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if (stillUsedVariables.isEmpty) {
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return code
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}
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val variablesWithAddressesTaken = code.flatMap {
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case AssemblyLine0(_, _, SubbyteConstant(MemoryAddressConstant(th), _)) => Some(th.name)
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case AssemblyLine0(_, WordImmediate, MemoryAddressConstant(th)) => Some(th.name)
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case _ => None
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}.toSet
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val localVariables = f.environment.getAllLocalVariables.filter {
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case v@MemoryVariable(name, typ, VariableAllocationMethod.Auto | VariableAllocationMethod.Register) =>
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typ.size == 1 && !paramVariables(name) && stillUsedVariables(name) && !variablesWithAddressesTaken(name) && !v.isVolatile
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case _ => false
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}
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if (localVariables.isEmpty) {
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return code
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}
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val variablesWithRegisterHint = f.environment.getAllLocalVariables.filter {
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case v@MemoryVariable(name, typ, VariableAllocationMethod.Register) =>
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typ.size == 1 && !paramVariables(name) && stillUsedVariables(name) && !variablesWithAddressesTaken(name) && !v.isVolatile
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case _ => false
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}.map(_.name).toSet
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val variablesWithLifetimes = localVariables.map(v =>
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v.name -> VariableLifetime.apply(v.name, code, expandToIncludeIndexing = true, expandToIncludeUsesOfLoadedIndices = Some(optimizationContext.niceFunctionProperties))
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).toMap
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val removeVariablesForReal = !options.flag(CompilationFlag.InternalCurrentlyOptimizingForMeasurement)
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val costFunction: CyclesAndBytes => Int = if (options.flag(CompilationFlag.OptimizeForSpeed)) _.cycles else _.bytes
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val importances = ReverseFlowAnalyzer.analyze(f, code, optimizationContext)
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val candidatePairs = for {
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x <- variablesWithLifetimes.toSeq :+ ("--" -> 0.until(0))
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y <- variablesWithLifetimes.toSeq :+ ("--" -> 0.until(0))
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vx = x._1
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vy = y._1
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if vx != vy
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if importances(x._2.start).x != Important
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if importances(y._2.start).y != Important
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range = if (x._2.isEmpty) y._2 else if (y._2.isEmpty) x._2 else (x._2.start min y._2.start) until (x._2.end max y._2.end)
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c <- canBeInlined(vx, vy, "-", "-", code.zip(importances).slice(range.start, range.end))
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bonusX = if (variablesWithRegisterHint(vx)) CyclesAndBytes(16, 16) else CyclesAndBytes.Zero
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bonusY = if (variablesWithRegisterHint(vy)) CyclesAndBytes(16, 16) else CyclesAndBytes.Zero
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} yield (x._1, y._1, range, c + bonusX + bonusY)
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//println(s"candidates: $candidatePairs")
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if (candidatePairs.isEmpty) {
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return code
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}
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val (bestX, bestY, range, _) = candidatePairs.maxBy(t => costFunction(t._4))
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log.debug(s"Inlining $bestX to register X and $bestY to register Y")
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val before = code.take(range.start)
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val after = code.drop(range.end)
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val oldCode = code.zip(importances).slice(range.start, range.end)
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val newCode = inlineVars(bestX, bestY, "-", "-", oldCode).result
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if (log.traceEnabled) {
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oldCode.foreach(l => log.trace(l._1.toString))
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log.trace(" ↓")
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newCode.foreach(l => log.trace(l.toString))
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}
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if (removeVariablesForReal) {
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if (bestX != "--" && contains(range, variablesWithLifetimes(bestX))) {
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f.environment.removeVariable(bestX)
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}
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if (bestY != "--" && contains(range, variablesWithLifetimes(bestY))) {
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f.environment.removeVariable(bestY)
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}
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}
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// TODO
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before ++ newCode ++ after
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}
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def contains(outer: Range, inner: Range): Boolean = {
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outer.contains(inner.start) && outer.contains(inner.end - 1)
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}
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// TODO: STA has different flag behaviour than TAX, keep it in mind!
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def canBeInlined(vx: String, vy: String, loadedX: String, loadedY: String, lines: List[(AssemblyLine, CpuImportance)]): Option[CyclesAndBytes] = {
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@inline
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def fail(i: Int): Option[CyclesAndBytes] = {
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// println(s"$vx and $vy failed because of $i")
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// lines.take(5).map(_._1).foreach(println)
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None
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}
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lines match {
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case (AssemblyLine0(_, Immediate, SubbyteConstant(MemoryAddressConstant(th), _)), _) :: xs
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if th.name == vx || th.name == vy =>
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// if an address of a variable is used, then that variable cannot be assigned to a register
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fail(0)
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case (AssemblyLine0(_, AbsoluteX | AbsoluteY | LongAbsoluteX |
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ZeroPageX | ZeroPageY |
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IndexedY | IndexedX | IndexedZ |
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LongIndexedY | LongIndexedZ |
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Indirect | LongIndirect |
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AbsoluteIndexedX, MemoryAddressConstant(th)), _) :: xs if th.name == vx || th.name == vy =>
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// if a variable is used as an array or a pointer, then it cannot be assigned to a register
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fail(1)
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case (AssemblyLine0(SEP | REP, Immediate, NumericConstant(nn, _)), _) :: xs =>
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if ((nn & 0x10) == 0) canBeInlined(vx, vy, loadedX, loadedY, xs)
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else fail(2)
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case (AssemblyLine0(SEP | REP, _, _), _) :: xs => fail(3)
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case (AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vx =>
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canBeInlined(vx, vy, loadedX, vx, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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case (AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vx =>
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canBeInlined(vx, vy, vx, loadedY, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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case (AssemblyLine0(LDY, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vy =>
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canBeInlined(vx, vy, loadedX, vy, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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case (AssemblyLine0(LDX, Absolute | ZeroPage, MemoryAddressConstant(th)), _) :: xs if th.name == vy =>
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canBeInlined(vx, vy, vy, loadedY, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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case (AssemblyLine0(LDX, _, constant), _) :: xs if "--" == vx && !constant.refersTo(vy) =>
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canBeInlined(vx, vy, "-", loadedY, xs)
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case (AssemblyLine0(LDY, _, constant), _) :: xs if "--" == vy && !constant.refersTo(vx) =>
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canBeInlined(vx, vy, loadedX, "-", xs)
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case (l@AssemblyLine0(STY, ZeroPage | Absolute, _), _) :: xs if loadedY == vx =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (l@AssemblyLine0(STX, ZeroPage | Absolute, _), _) :: xs if loadedX == vy =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (l@AssemblyLine0(_,_, _), _) :: _ if l.concernsX && loadedX == vy =>
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fail(71)
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case (l@AssemblyLine0(_,_, _), _) :: _ if l.concernsY && loadedY == vx =>
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fail(72)
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case (AssemblyLine0(_, AbsoluteX, _), _) :: xs if loadedX == vx || vx == "--" && loadedX == "-" =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (AssemblyLine0(op, AbsoluteX, _), _) :: xs if loadedX == vy =>
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if (hasBothIndexingModes(op)) {
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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} else fail(4)
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case (AssemblyLine0(_, AbsoluteY, _), _) :: xs if loadedY == vy || vy == "--" && loadedY == "-" =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (AssemblyLine0(op, AbsoluteY, _), _) :: xs if loadedY == vx =>
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if (hasBothIndexingModes(op)) {
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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} else fail(5)
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case (AssemblyLine0(op, IndexedY | IndexedSY | ZeroPageY, _), _) :: xs if loadedY == vy || vy == "--" && loadedY == "-" =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (AssemblyLine0(op, IndexedX | ZeroPageX | LongAbsoluteX, _), _) :: xs if loadedX == vx || vx == "--" && loadedX == "-" =>
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canBeInlined(vx, vy, loadedX, loadedY, xs)
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case (AssemblyLine0(_, IndexedX | ZeroPageX | LongAbsoluteX | IndexedY | IndexedSY | ZeroPageY | AbsoluteX | AbsoluteY, _), _) :: xs =>
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fail(6)
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case (AssemblyLine(INC | DEC, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == vx =>
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// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
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if (elidability == Elidability.Elidable) {
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canBeInlined(vx, vy, "-", loadedY, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
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} else fail(7)
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case (AssemblyLine(INC | DEC, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == vy =>
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// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
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if (elidability == Elidability.Elidable) {
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canBeInlined(vx, vy, loadedX, "-", xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 4))
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} else fail(8)
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case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == vx || th.name == vy =>
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// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
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if (elidability == Elidability.Elidable) {
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canBeInlined(vx, vy, loadedX, loadedY, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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} else fail(9)
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case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == vx =>
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// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
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if (elidability == Elidability.Elidable) {
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canBeInlined(vx, vy, "-", loadedY, xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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} else fail(10)
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case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), elidability, _), _) :: xs if th.name == vy =>
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// changing LDA->TXA, STA->TAX, INC->INX, DEC->DEX saves 2 bytes
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if (elidability == Elidability.Elidable) {
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canBeInlined(vx, vy, loadedX, "-", xs).map(_ + CyclesAndBytes(bytes = 2, cycles = 2))
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} else fail(11)
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case (AssemblyLine0(_, _, MemoryAddressConstant(th)), _) :: xs if th.name == vx || th.name == vy =>
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fail(12)
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case (AssemblyLine0(_, _, SubbyteConstant(MemoryAddressConstant(th), _)), _) :: xs if th.name == vx || th.name == vy =>
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fail(13)
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case (AssemblyLine0(op, _, _), _) :: xs if OpcodeClasses.ConcernsXAlways(op) =>
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fail(14)
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case (AssemblyLine0(op, _, _), _) :: xs if OpcodeClasses.ConcernsYAlways(op) =>
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fail(15)
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case (AssemblyLine0(op, _, _), _) :: xs if opcodesThatAlwaysPrecludeAllocation(op) =>
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fail(16)
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case (AssemblyLine0(LABEL | JSR, _, _), _) :: xs =>
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// labels always end the initial section
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canBeInlined(vx, vy, "-", "-", xs)
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case (AssemblyLine0(op, _, _), _) :: xs if OpcodeClasses.AllDirectJumps(op) =>
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// labels always end the initial section
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canBeInlined(vx, vy, "-", "-", xs)
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case _ :: xs => canBeInlined(vx, vy, loadedX, loadedY, xs)
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case Nil => Some(CyclesAndBytes.Zero)
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}
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}
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def inlineVars(vx: String,
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vy: String,
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loadedX: String,
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loadedY: String,
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lines: List[(AssemblyLine, CpuImportance)]): TailRec[List[AssemblyLine]] = {
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lines match {
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case (AssemblyLine(INC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vx =>
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tailcall(inlineVars(vx, vy, "-", loadedY, xs)).map( AssemblyLine.implied(INX).pos(s) :: _)
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case (AssemblyLine(INC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vy =>
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tailcall(inlineVars(vx, vy, loadedX, "-", xs)).map(AssemblyLine.implied(INY).pos(s) :: _)
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case (AssemblyLine(DEC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vx =>
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tailcall(inlineVars(vx, vy, "-", loadedY, xs)).map(AssemblyLine.implied(DEX).pos(s) :: _)
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case (AssemblyLine(DEC, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vy =>
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tailcall(inlineVars(vx, vy, loadedX, "-", xs)).map(AssemblyLine.implied(DEY).pos(s) :: _)
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case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
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if th.name == vx =>
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if (imp.z == Unimportant && imp.n == Unimportant) {
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tailcall(inlineVars(vx, vy, vx, loadedY, xs))
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} else if (imp.c == Unimportant) {
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tailcall(inlineVars(vx, vy, vx, loadedY, xs)).map(AssemblyLine.immediate(CPX, 0).pos(s) :: _)
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} else {
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tailcall(inlineVars(vx, vy, vx, loadedY, xs)).map(AssemblyLine.implied(INX).pos(s) :: AssemblyLine.implied(DEX).pos(s) :: _)
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}
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case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
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if th.name == vx =>
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if (imp.z == Unimportant && imp.n == Unimportant) {
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tailcall(inlineVars(vx, vy, loadedX, vx, xs))
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} else if (imp.c == Unimportant) {
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tailcall(inlineVars(vx, vy, loadedX, vx, xs)).map(AssemblyLine.immediate(CPX, 0).pos(s) :: _)
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} else {
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tailcall(inlineVars(vx, vy, loadedX, vy, xs)).map(AssemblyLine.implied(INX).pos(s) :: AssemblyLine.implied(DEX).pos(s) :: _)
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}
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case (AssemblyLine(LDY, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
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if th.name == vy =>
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if (imp.z == Unimportant && imp.n == Unimportant) {
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inlineVars(vx, vy, loadedX, vy, xs)
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} else if (imp.c == Unimportant) {
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tailcall(inlineVars(vx, vy, loadedX, vy, xs)).map(AssemblyLine.immediate(CPY, 0).pos(s) :: _)
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} else {
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tailcall(inlineVars(vx, vy, loadedX, vy, xs)).map(AssemblyLine.implied(INY).pos(s) :: AssemblyLine.implied(DEY).pos(s) :: _)
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}
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case (AssemblyLine(LDX, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), imp) :: xs
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if th.name == vy =>
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if (imp.z == Unimportant && imp.n == Unimportant) {
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inlineVars(vx, vy, vy, loadedY, xs)
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} else if (imp.c == Unimportant) {
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tailcall(inlineVars(vx, vy, vy, loadedY, xs)).map(AssemblyLine.immediate(CPY, 0).pos(s) :: _)
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} else {
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tailcall(inlineVars(vx, vy, vy, loadedY, xs)).map(AssemblyLine.implied(INY).pos(s) :: AssemblyLine.implied(DEY).pos(s) :: _)
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}
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case (x@AssemblyLine(LDY, _, _, _, _), imp) :: xs =>
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inlineVars(vx, vy, loadedX, "-", xs).map(x :: _)
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case (x@AssemblyLine(LDX, _, _, _, _), imp) :: xs =>
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inlineVars(vx, vy, "-", loadedY, xs).map(x :: _)
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case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vx =>
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tailcall(inlineVars(vx, vy, vx, loadedY, xs)).map(AssemblyLine.implied(TXA).pos(s) :: _)
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case (AssemblyLine(LDA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vy =>
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tailcall(inlineVars(vx, vy, loadedX, vy, xs)).map(AssemblyLine.implied(TYA).pos(s) :: _)
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case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vx =>
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tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(AssemblyLine.implied(TAX).pos(s) :: _)
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case (AssemblyLine(STA, Absolute | ZeroPage, MemoryAddressConstant(th), _, s), _) :: xs
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if th.name == vy =>
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tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(AssemblyLine.implied(TAY).pos(s) :: _)
|
|
|
|
case (l@AssemblyLine0(_, AbsoluteX, _), _) :: xs if loadedX == vy =>
|
|
tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(l.copy(addrMode = AbsoluteY) :: _)
|
|
|
|
case (l@AssemblyLine0(_, AbsoluteY, _), _) :: xs if loadedY == vx =>
|
|
tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(l.copy(addrMode = AbsoluteX) :: _)
|
|
|
|
case (l@AssemblyLine0(STY, ZeroPage | Absolute, _), _) :: xs if loadedY == vx =>
|
|
tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(l.copy(opcode = STX) :: _)
|
|
|
|
case (l@AssemblyLine0(STX, ZeroPage | Absolute, _), _) :: xs if loadedX == vy =>
|
|
tailcall(inlineVars(vx, vy, loadedX, loadedY, xs)).map(l.copy(opcode = STY) :: _)
|
|
|
|
case (x, _) :: xs => inlineVars(vx, vy, loadedX, loadedY, xs).map(x :: _)
|
|
|
|
case Nil => done(Nil)
|
|
}
|
|
}
|
|
|
|
}
|