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502 lines
28 KiB
Scala
502 lines
28 KiB
Scala
package millfork.assembly.z80.opt
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import millfork.assembly.z80._
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import millfork.assembly.{AssemblyOptimization, OptimizationContext}
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import millfork.env._
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import millfork.node.ZRegister
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import millfork.{CompilationFlag, NonOverlappingIntervals}
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import scala.collection.mutable.ListBuffer
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/**
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* @author Karol Stasiak
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*/
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object ByteVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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override def requiredFlags: Set[CompilationFlag.Value] = Set(CompilationFlag.RegisterVariables)
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override def name = "Allocating variables to single registers"
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override def minimumRequiredLines: Int = 3
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object CyclesAndBytes {
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val Zero = CyclesAndBytes(0, 0)
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}
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case class CyclesAndBytes(bytes: Int, cycles: Int) {
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def +(that: CyclesAndBytes) = CyclesAndBytes(this.bytes + that.bytes, this.cycles + that.cycles)
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def *(scale: Double) = CyclesAndBytes(bytes.*(scale).round.toInt, cycles.*(scale).round.toInt)
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}
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override def optimize(f: NormalFunction, code: List[ZLine], optimizationContext: OptimizationContext): List[ZLine] = {
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val vs = VariableStatus(f, code, optimizationContext, _.size == 1, allowParams = true).getOrElse(return code)
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val options = optimizationContext.options
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val useIx = options.flag(CompilationFlag.UseIxForStack)
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val useIy = options.flag(CompilationFlag.UseIyForStack)
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val log = options.log
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val removeVariablesForReal = !options.flag(CompilationFlag.InternalCurrentlyOptimizingForMeasurement)
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val costFunction: CyclesAndBytes => Int = if (options.flag(CompilationFlag.OptimizeForSpeed)) _.cycles else _.bytes
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lazy val savingsForRemovingOneStackVariable = {
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val localVariableAreaSize = code.flatMap {
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case ZLine0(_, OneRegisterOffset(ZRegister.MEM_IX_D, offset), _) if useIx => Some(offset)
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case ZLine0(_, TwoRegistersOffset(_, ZRegister.MEM_IX_D, offset), _) if useIx => Some(offset)
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case ZLine0(_, TwoRegistersOffset(ZRegister.MEM_IX_D, _, offset), _) if useIx => Some(offset)
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case ZLine0(_, OneRegisterOffset(ZRegister.MEM_IY_D, offset), _) if useIy => Some(offset)
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case ZLine0(_, TwoRegistersOffset(_, ZRegister.MEM_IY_D, offset), _) if useIy => Some(offset)
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case ZLine0(_, TwoRegistersOffset(ZRegister.MEM_IY_D, _, offset), _) if useIy => Some(offset)
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case _ => None
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}.toSet.size
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val prologueAndEpilogue = if (f.returnType.size == 2) CyclesAndBytes(107, 20) else CyclesAndBytes(95, 17)
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localVariableAreaSize match {
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case 1 => prologueAndEpilogue
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case 2 => prologueAndEpilogue * 0.4
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case 3 => prologueAndEpilogue * 0.1
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case _ => CyclesAndBytes.Zero
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}
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}
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val bCandidates = getCandidates(vs, _.b, ZRegister.B, savingsForRemovingOneStackVariable, useIx, useIy)
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val cCandidates = getCandidates(vs, _.c, ZRegister.C, savingsForRemovingOneStackVariable, useIx, useIy)
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val dCandidates = getCandidates(vs, _.d, ZRegister.D, savingsForRemovingOneStackVariable, useIx, useIy)
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val eCandidates = getCandidates(vs, _.e, ZRegister.E, savingsForRemovingOneStackVariable, useIx, useIy)
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val hCandidates = getCandidates(vs, _.h, ZRegister.H, savingsForRemovingOneStackVariable, useIx, useIy)
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val lCandidates = getCandidates(vs, _.l, ZRegister.L, savingsForRemovingOneStackVariable, useIx, useIy)
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val bCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](bCandidates, _._2.start, _._2.end)
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val cCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](cCandidates, _._2.start, _._2.end)
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val dCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](dCandidates, _._2.start, _._2.end)
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val eCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](eCandidates, _._2.start, _._2.end)
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val hCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](hCandidates, _._2.start, _._2.end)
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val lCandidateSets = NonOverlappingIntervals.apply[(String, Range, CyclesAndBytes)](lCandidates, _._2.start, _._2.end)
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val variants = for {
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vb <- if (options.flag(CompilationFlag.SingleThreaded)) bCandidateSets else bCandidateSets.par
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nb = vb.map(_._1)
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vc <- cCandidateSets
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nc = vc.map(_._1)
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if (nb & nc).isEmpty
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vd <- dCandidateSets
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nd = vd.map(_._1)
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if (nb & nd).isEmpty
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if (nc & nd).isEmpty
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ve <- eCandidateSets
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ne = ve.map(_._1)
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if (nb & ne).isEmpty
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if (nc & ne).isEmpty
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if (nd & ne).isEmpty
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vh <- hCandidateSets
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nh = vh.map(_._1)
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if (nb & nh).isEmpty
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if (nc & nh).isEmpty
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if (nd & nh).isEmpty
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if (ne & nh).isEmpty
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vl <- lCandidateSets
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nl = vl.map(_._1)
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if (nb & nl).isEmpty
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if (nc & nl).isEmpty
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if (nd & nl).isEmpty
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if (ne & nl).isEmpty
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if (nh & nl).isEmpty
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score = vb.toSeq.map(x => costFunction(x._3)).sum +
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vc.toSeq.map(x => costFunction(x._3)).sum +
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vd.toSeq.map(x => costFunction(x._3)).sum +
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ve.toSeq.map(x => costFunction(x._3)).sum +
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vh.toSeq.map(x => costFunction(x._3)).sum +
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vl.toSeq.map(x => costFunction(x._3)).sum
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} yield (score, vb, vc, vd, ve, vh, vl)
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if (variants.isEmpty) {
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return code
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}
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// variants.foreach(println)
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val (_, bestBs, bestCs, bestDs, bestEs, bestHs, bestLs) = variants.maxBy(_._1)
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def reportOptimizedBlock[T](oldCode: List[(T, ZLine)], newCode: List[ZLine]): Unit = {
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if (log.traceEnabled) {
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oldCode.foreach(l => log.trace(l._2.toString))
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log.trace(" ↓")
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newCode.foreach(l => log.trace(l.toString))
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}
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}
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if (bestBs.nonEmpty || bestCs.nonEmpty || bestDs.nonEmpty || bestEs.nonEmpty || bestHs.nonEmpty || bestLs.nonEmpty) {
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val output = ListBuffer[ZLine]()
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var i = 0
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@inline
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def tryInline(bests: Set[(String, Range, CyclesAndBytes)], register: ZRegister.Value): Boolean = {
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bests.find(_._2.start == i).exists {
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case (v, range, _) =>
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log.debug(s"Inlining $v to single register $register")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars(v, register, addressInHl = false, addressInBc = false, addressInDe = false, oldCode.map(_._2))
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reportOptimizedBlock(oldCode, newCode)
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if (vs.paramVariables(v)) {
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val variable = vs.localVariables.find(_.name.==(v)).get.asInstanceOf[MemoryVariable]
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val addr = variable.toAddress
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if (register == ZRegister.A) {
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output += ZLine.ldAbs8(ZRegister.A, addr, elidability = ZLine.elidability(variable))
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} else {
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output += ZLine.ldAbs8(ZRegister.A, addr, elidability = ZLine.elidability(variable))
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output += ZLine.ld8(register, ZRegister.A)
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}
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}
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output ++= newCode
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i = range.end
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if (removeVariablesForReal &&
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!v.startsWith("IX+") &&
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!v.startsWith("IY+") &&
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!v.startsWith("SP+") &&
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vs.variablesWithLifetimesMap.contains(v) &&
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contains(range, vs.variablesWithLifetimesMap(v))) {
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if (!vs.paramVariables(v)) f.environment.removeVariable(v)
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}
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true
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case _ => false
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}
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}
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while (i < code.length) {
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var done = false
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done = tryInline(bestBs, ZRegister.B)
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if (!done) {
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done = tryInline(bestCs, ZRegister.C)
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}
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if (!done) {
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done = tryInline(bestDs, ZRegister.D)
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}
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if (!done) {
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done = tryInline(bestEs, ZRegister.E)
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}
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if (!done) {
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done = tryInline(bestHs, ZRegister.H)
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}
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if (!done) {
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done = tryInline(bestLs, ZRegister.L)
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}
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if (!done) {
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output += code(i)
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i += 1
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}
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}
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output.toList
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} else {
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code
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}
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}
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private def getCandidates(vs: VariableStatus, importanceExtractor: CpuImportance => Importance, register: ZRegister.Value, savingsForRemovingOneStackVariable: =>CyclesAndBytes, useIx: Boolean, useIy: Boolean): Seq[(String, Range, CyclesAndBytes)] = {
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vs.variablesWithLifetimes.filter {
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case (v, range) =>
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val tuple = vs.codeWithFlow(range.start)
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importanceExtractor(tuple._1.importanceAfter) != Important || {
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// println(s"Cannot inline ${v.name} to $register because of early $tuple")
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false
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}
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}.flatMap {
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case (v, range) =>
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val id = v match {
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case MemoryVariable(name, _, _) => name
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case StackVariable(_, _, offset) if useIx => "IX+" + offset
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case StackVariable(_, _, offset) if useIy => "IY+" + offset
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case StackVariable(_, _, offset) => "SP+" + offset
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}
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var bonus = CyclesAndBytes.Zero
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if (vs.variablesWithRegisterHint(v.name)) bonus += CyclesAndBytes(16, 16)
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if (vs.paramVariables(v.name)) bonus += (if (register == ZRegister.A) CyclesAndBytes(-13, -3) else CyclesAndBytes(-17, -4))
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if (id.startsWith("IX+") || id.startsWith("IY+")) bonus += savingsForRemovingOneStackVariable
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if (id.startsWith("SP+") || v.isVolatile) None
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else canBeInlined(id, synced = false, register, Some(false), Some(false), Some(false), vs.codeWithFlow.slice(range.start, range.end)).map { score =>
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(id, range, score + bonus)
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}
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}
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}
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def okPrefix(vs: VariableStatus, v: Variable, range: Range, reg: ZRegister.Value): Boolean = {
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if (!vs.paramVariables(v.name)) return true
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if (vs.paramRegs.contains(reg)) {
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// println(s"okPrefix $v false: reg $reg in use")
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return false
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}
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if (range.size < 2) {
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// println(s"okPrefix $v false: range $range too small")
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return false
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}
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if (range.start < 1) {
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// println(s"okPrefix $v true: range $range early enough")
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return true
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}
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import ZOpcode._
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vs.codeWithFlow.take(range.start) match {
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case Nil =>
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case (_, ZLine0(LABEL, _, _)) :: xs =>
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if (xs.exists { case (_, l) => l.opcode == LABEL || ZOpcodeClasses.NonLinear(l.opcode) }) {
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// println(s"okPrefix false: LABEL in prefix")
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return false
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}
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case _ => return false
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}
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vs.codeWithFlow(range.start - 1)._1.importanceAfter.getRegister(reg) == Unimportant
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}
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def contains(outer: Range, inner: Range): Boolean = {
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outer.contains(inner.start) && outer.contains(inner.end - 1)
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}
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import millfork.assembly.z80.ZOpcode._
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import millfork.node.ZRegister._
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def add(first: Boolean, ifTrue: CyclesAndBytes, ifFalse: CyclesAndBytes): CyclesAndBytes => CyclesAndBytes =
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if (first) _ + ifTrue else _ + ifFalse
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def add(value: CyclesAndBytes): CyclesAndBytes=>CyclesAndBytes = _ + value
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def canBeInlined(vname: String, synced: Boolean, target: ZRegister.Value, addressInHl: Option[Boolean], addressInBc: Option[Boolean], addressInDe: Option[Boolean], code: List[(FlowInfo, ZLine)]): Option[CyclesAndBytes] = {
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def fail(reason: Int): None.type = {
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// println(s"Cannot inline $vname to $target because of [[$reason]] ${code.head}")
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None
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}
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object NotTarget {
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def unapply(r: ZRegister.Value): Option[ZRegister.Value] = if (r == target) None else Some(r)
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}
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object ThisVar {
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def unapply(c: Constant): Option[Constant] = c match {
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case MemoryAddressConstant(th) if th.name == vname => Some(c)
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case _ => None
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}
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}
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object ThisOffsetX {
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def unapply(c: Int): Option[Int] = if ("IX+" + c == vname) Some(c) else None
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}
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object ThisOffsetY {
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def unapply(c: Int): Option[Int] = if ("IY+" + c == vname) Some(c) else None
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}
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code match {
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case (_, ZLine0(LD_16, TwoRegisters(HL | IY, SP), _)) :: _ if vname.startsWith("IX+") => fail(121)
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case (_, ZLine0(LD_16, TwoRegisters(HL | IX, SP), _)) :: _ if vname.startsWith("IY+") => fail(121)
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case (_, ZLine0(LD_16, TwoRegisters(SP, HL | IY), _)) :: _ if vname.startsWith("IX+") => fail(122)
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case (_, ZLine0(LD_16, TwoRegisters(SP, HL | IX), _)) :: _ if vname.startsWith("IY+") => fail(122)
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case (_, ZLine0(ADD_16 | SBC_16, TwoRegisters(HL | IY, SP), _)) :: _ if vname.startsWith("IX+") => fail(123)
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case (_, ZLine0(ADD_16 | SBC_16, TwoRegisters(HL | IX, SP), _)) :: _ if vname.startsWith("IY+") => fail(123)
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case (_, ZLine0(LD_HLSP | LD_DESP, _, _)) :: _ if vname.contains("+") => fail(124)
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case (_, ZLine0(EX_SP, _, _)) :: _ if vname.contains("+") => fail(125)
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case (_, ZLine0(LD, TwoRegisters(A, MEM_ABS_8), ThisVar(_))) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(9, 2)))
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case (_, ZLine0(LD, TwoRegisters(MEM_ABS_8, A), ThisVar(_))) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(9, 2)))
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case (_, ZLine0(LD, TwoRegistersOffset(reg, MEM_IX_D, ThisOffsetX(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(reg == target, CyclesAndBytes(19, 3), CyclesAndBytes(15, 2)))
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case (_, ZLine0(LD, TwoRegistersOffset(MEM_IX_D, reg, ThisOffsetX(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(reg == target, CyclesAndBytes(19, 3), CyclesAndBytes(15, 2)))
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case (_, ZLine0(_, OneRegisterOffset(MEM_IX_D, ThisOffsetX(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(15, 2)))
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case (_, ZLine0(LD, TwoRegistersOffset(reg, MEM_IY_D, ThisOffsetY(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(reg == target, CyclesAndBytes(19, 3), CyclesAndBytes(15, 2)))
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case (_, ZLine0(LD, TwoRegistersOffset(MEM_IY_D, reg, ThisOffsetY(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(reg == target, CyclesAndBytes(19, 3), CyclesAndBytes(15, 2)))
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case (_, ZLine0(_, OneRegisterOffset(MEM_IY_D, ThisOffsetY(_)), _)) :: xs =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(15, 2)))
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case (_, ZLine0(LD_16, TwoRegisters(HL, IMM_16), ThisVar(_))) :: xs =>
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if (target == H || target == L) fail(61) else
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(10, 3)))
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case (_, ZLine0(LD_16, TwoRegisters(BC, IMM_16), ThisVar(_))) :: xs =>
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if (target == B || target == C) fail(61) else
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canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(true), addressInDe, xs).map(add(CyclesAndBytes(10, 3)))
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case (_, ZLine0(LD_16, TwoRegisters(DE, IMM_16), ThisVar(_))) :: xs =>
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if (target == D || target == E) fail(61) else
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(10, 3)))
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// TODO: other combinations:
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case (_, ZLine0(LD, TwoRegisters(L, C), _)) :: (_, ZLine0(LD, TwoRegisters(H, B), _)) :: xs if addressInBc.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(H, B), _)) :: (_, ZLine0(LD, TwoRegisters(L, C), _)) :: xs if addressInBc.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(L, E), _)) :: (_, ZLine0(LD, TwoRegisters(H, D), _)) :: xs if addressInDe.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(H, D), _)) :: (_, ZLine0(LD, TwoRegisters(L, E), _)) :: xs if addressInDe.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl = Some(true), addressInBc, addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(C, L), _)) :: (_, ZLine0(LD, TwoRegisters(B, H), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(true), addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(B, H), _)) :: (_, ZLine0(LD, TwoRegisters(C, L), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(true), addressInDe, xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(E, L), _)) :: (_, ZLine0(LD, TwoRegisters(D, H), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(LD, TwoRegisters(D, H), _)) :: (_, ZLine0(LD, TwoRegisters(E, L), _)) :: xs if addressInHl.contains(true) =>
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canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(true), xs).map(add(CyclesAndBytes(8, 2)))
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case (_, ZLine0(_, OneRegister(MEM_HL), _)) :: xs => addressInHl match {
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case Some(true) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(3, 0)))
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case Some(false) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
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case None => fail(70)
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}
|
|
|
|
case (_, ZLine0(LD, TwoRegisters(MEM_HL, NotTarget(_)) | TwoRegisters(NotTarget(_), MEM_HL), _)) :: xs => addressInHl match {
|
|
case Some(true) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(3, 0)))
|
|
case Some(false) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case None => fail(71)
|
|
}
|
|
case (_, ZLine0(LD, TwoRegisters(MEM_BC, NotTarget(_)) | TwoRegisters(NotTarget(_), MEM_BC), _)) :: xs => addressInBc match {
|
|
case Some(true) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(3, 0)))
|
|
case Some(false) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case None => fail(72)
|
|
}
|
|
case (_, ZLine0(LD, TwoRegisters(MEM_DE, NotTarget(_)) | TwoRegisters(NotTarget(_), MEM_DE), _)) :: xs => addressInDe match {
|
|
case Some(true) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(3, 0)))
|
|
case Some(false) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case None => fail(73)
|
|
}
|
|
|
|
case (_, ZLine0(_, _, SubbyteConstant(ThisVar(_), _))) :: _ => fail(6)
|
|
case (_, ZLine0(_, _, ThisVar(_))) :: _ => fail(4)
|
|
case (_, ZLine0(_, _, CompoundConstant(_, ThisVar(_), _))) :: _ => fail(5)
|
|
|
|
case (_, ZLine0(CALL, _, _)) :: xs =>
|
|
// TODO: check return type and allow HL sometimes
|
|
target match {
|
|
case ZRegister.B | ZRegister.C | ZRegister.D | ZRegister.E =>
|
|
canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs).map(add(CyclesAndBytes(-21, -2)))
|
|
case _ =>
|
|
fail(3)
|
|
}
|
|
|
|
case (_, x) :: xs if x.changesRegister(target) => fail(1)
|
|
case (_, x) :: xs if x.readsRegister(target) && !synced => fail(2)
|
|
|
|
// TODO: tossing addresses around:
|
|
// case (_, ZLine0(LD, TwoRegisters(H, B), _)) :: (_, ZLine0(LD, TwoRegisters(L, C), _)) :: xs =>
|
|
|
|
|
|
case (_, x) :: xs if x.changesRegister(HL) => canBeInlined(vname, synced, target, addressInHl = Some(false), addressInBc, addressInDe, xs)
|
|
case (_, x) :: xs if x.changesRegister(BC) => canBeInlined(vname, synced, target, addressInHl, addressInBc = Some(false), addressInDe, xs)
|
|
case (_, x) :: xs if x.changesRegister(DE) => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe = Some(false), xs)
|
|
|
|
case (_, x) :: xs if x.readsRegister(HL) && addressInHl.contains(true) => fail(81)
|
|
case (_, x) :: xs if x.readsRegister(BC) && addressInBc.contains(true) => fail(82)
|
|
case (_, x) :: xs if x.readsRegister(DE) && addressInDe.contains(true) => fail(83)
|
|
|
|
case (_, ZLine0(LABEL, _, _)) :: xs => canBeInlined(vname, synced = false, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case _ :: xs => canBeInlined(vname, synced, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case _ => Some(CyclesAndBytes.Zero)
|
|
}
|
|
}
|
|
|
|
def inlineVars(vname: String, target: ZRegister.Value, addressInHl: Boolean, addressInBc: Boolean, addressInDe: Boolean, code: List[ZLine]): List[ZLine] = {
|
|
// if (code.nonEmpty) println(code.head)
|
|
code match {
|
|
case ZLine(LD, TwoRegisters(A, MEM_ABS_8), MemoryAddressConstant(th), _, s) :: xs if th.name == vname =>
|
|
ZLine.ld8(A, target).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case ZLine(LD, TwoRegisters(MEM_ABS_8, A), MemoryAddressConstant(th), _, s) :: xs if th.name == vname =>
|
|
ZLine.ld8(target, A).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case ZLine(LD, TwoRegistersOffset(reg, MEM_IX_D, off), _, _, s) :: xs if "IX+" + off == vname =>
|
|
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
else ZLine.ld8(reg, target).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case ZLine(LD, TwoRegistersOffset(MEM_IX_D, IMM_8, off), param, _, s) :: xs if "IX+" + off == vname =>
|
|
ZLine.ldImm8(target, param).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case ZLine(LD, TwoRegistersOffset(MEM_IX_D, reg, off), _, _, s) :: xs if "IX+" + off == vname =>
|
|
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
else ZLine.ld8(target, reg).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case (l@ZLine0(_, OneRegisterOffset(MEM_IX_D, off), _)) :: xs if "IX+" + off == vname =>
|
|
l.copy(registers = OneRegister(target)) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case ZLine(LD, TwoRegistersOffset(reg, MEM_IY_D, off), _, _, s) :: xs if "IY+" + off == vname =>
|
|
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
else ZLine.ld8(reg, target).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case ZLine(LD, TwoRegistersOffset(MEM_IY_D, IMM_8, off), param, _, s) :: xs if "IY+" + off == vname =>
|
|
ZLine.ldImm8(target, param).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case ZLine(LD, TwoRegistersOffset(MEM_IY_D, reg, off), _, _, s) :: xs if "IY+" + off == vname =>
|
|
if (reg == target) inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
else ZLine.ld8(target, reg).pos(s) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case (l@ZLine0(_, OneRegisterOffset(MEM_IY_D, off), _)) :: xs if "IY+" + off == vname =>
|
|
l.copy(registers = OneRegister(target)) :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case ZLine0(LD_16, TwoRegisters(HL, IMM_16), MemoryAddressConstant(th)) :: xs if th.name == vname =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc, addressInDe, xs)
|
|
case ZLine0(LD_16, TwoRegisters(BC, IMM_16), MemoryAddressConstant(th)) :: xs if th.name == vname =>
|
|
inlineVars(vname, target, addressInHl, addressInBc = true, addressInDe, xs)
|
|
case ZLine0(LD_16, TwoRegisters(DE, IMM_16), MemoryAddressConstant(th)) :: xs if th.name == vname =>
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe = true, xs)
|
|
|
|
case (x@ZLine0(_, OneRegister(MEM_HL), _)) :: xs if addressInHl =>
|
|
x.copy(registers = OneRegister(target)) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case (x@ZLine0(LD, TwoRegisters(MEM_HL, reg), p)) :: xs if addressInHl =>
|
|
x.copy(registers = TwoRegisters(target, reg), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case (x@ZLine0(LD, TwoRegisters(reg, MEM_HL), p)) :: xs if addressInHl =>
|
|
x.copy(registers = TwoRegisters(reg, target), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case (x@ZLine0(LD, TwoRegisters(MEM_BC, reg), p)) :: xs if addressInBc =>
|
|
x.copy(registers = TwoRegisters(target, reg), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case (x@ZLine0(LD, TwoRegisters(reg, MEM_BC), p)) :: xs if addressInBc =>
|
|
x.copy(registers = TwoRegisters(reg, target), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
case (x@ZLine0(LD, TwoRegisters(MEM_DE, reg), p)) :: xs if addressInDe =>
|
|
x.copy(registers = TwoRegisters(target, reg), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case (x@ZLine0(LD, TwoRegisters(reg, MEM_DE), p)) :: xs if addressInDe =>
|
|
x.copy(registers = TwoRegisters(reg, target), parameter = p) ::
|
|
inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
|
|
// TODO: other combinations
|
|
case ZLine0(LD, TwoRegisters(L, C), _) :: ZLine0(LD, TwoRegisters(H, B), _) :: xs if addressInBc =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
|
|
case ZLine0(LD, TwoRegisters(H, B), _) :: ZLine0(LD, TwoRegisters(L, C), _) :: xs if addressInBc =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
|
|
case ZLine0(LD, TwoRegisters(L, E), _) :: ZLine0(LD, TwoRegisters(H, D), _) :: xs if addressInDe =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
|
|
case ZLine0(LD, TwoRegisters(H, D), _) :: ZLine0(LD, TwoRegisters(L, E), _) :: xs if addressInDe =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
|
|
|
|
case ZLine0(LD, TwoRegisters(C, L), _) :: ZLine0(LD, TwoRegisters(B, H), _) :: xs if addressInHl =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
|
|
case ZLine0(LD, TwoRegisters(B, H), _) :: ZLine0(LD, TwoRegisters(C, L), _) :: xs if addressInHl =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = true, addressInDe = addressInDe, xs)
|
|
case ZLine0(LD, TwoRegisters(E, L), _) :: ZLine0(LD, TwoRegisters(D, H), _) :: xs if addressInHl =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
|
|
case ZLine0(LD, TwoRegisters(D, H), _) :: ZLine0(LD, TwoRegisters(E, L), _) :: xs if addressInHl =>
|
|
inlineVars(vname, target, addressInHl = true, addressInBc = addressInBc, addressInDe = true, xs)
|
|
|
|
case (x@ZLine(CALL,_,_,_,s))::xs =>
|
|
// TODO: this push/pull pair shouldn't prevent the inlining to the other register in the pair
|
|
target match {
|
|
case ZRegister.B | ZRegister.C =>
|
|
ZLine.register(PUSH, BC).pos(s) :: x :: ZLine.register(POP, BC).pos(s) ::
|
|
inlineVars(vname, target, addressInHl = false, addressInBc, addressInDe = false, xs)
|
|
case ZRegister.D | ZRegister.E =>
|
|
ZLine.register(PUSH, DE).pos(s) :: x :: ZLine.register(POP, DE).pos(s) ::
|
|
inlineVars(vname, target, addressInHl = false, addressInBc = false, addressInDe, xs)
|
|
}
|
|
|
|
case x :: xs if x.changesRegister(HL) =>
|
|
x :: inlineVars(vname, target, addressInHl = false, addressInBc, addressInDe, xs)
|
|
case x :: xs if x.changesRegister(BC) =>
|
|
x :: inlineVars(vname, target, addressInHl, addressInBc = false, addressInDe, xs)
|
|
case x :: xs if x.changesRegister(DE) =>
|
|
x :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe = false, xs)
|
|
|
|
case x :: _ if x.changesRegister(target) => ???
|
|
case x :: xs => x :: inlineVars(vname, target, addressInHl, addressInBc, addressInDe, xs)
|
|
case Nil => Nil
|
|
}
|
|
}
|
|
}
|